公开(公告)号：US10304961B2

公开(公告)日：2019-05-28

申请号：US15604934

申请日：2017-05-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daisuke Matsubayashi ,  Yoshiyuki Kobayashi ,  Shuhei Nagatsuka ,  Yutaka Shionoiri

IPC: H01L29/786

Abstract: A transistor having favorable electrical characteristics. A transistor suitable for miniaturization. A transistor having a high switching speed. One embodiment of the present invention is a semiconductor device that includes a transistor. The transistor includes an oxide semiconductor, a gate electrode, and a gate insulator. The oxide semiconductor includes a first region in which the oxide semiconductor and the gate electrode overlap with each other with the gate insulator positioned therebetween. The transistor has a threshold voltage higher than 0 V and a switching speed lower than 100 nanoseconds.

公开(公告)号：US10050060B2

公开(公告)日：2018-08-14

申请号：US15591145

申请日：2017-05-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidekazu Miyairi ,  Yuichi Sato ,  Yuji Asano ,  Tetsunori Maruyama ,  Tatsuya Onuki ,  Shuhei Nagatsuka

IPC: H01L27/12 ,  H01L29/78 ,  H01L23/48 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L27/06 ,  H01L29/786 ,  H01L21/768 ,  H01L21/8258

Abstract: To provide a semiconductor device with excellent electrical characteristics or a semiconductor device with stable electrical characteristics. A semiconductor device includes a first transistor, a second transistor, a first insulator, a second insulator, a first wiring, and a first plug. The first transistor includes silicon. The second transistor includes an oxide semiconductor. The first insulator is located over the first transistor. The second insulator is located over the first insulator. The second transistor is located over the second insulator. The first wiring is located over the second insulator and the first plug. The first transistor and the second transistor are electrically connected to each other through the first wiring and the first plug. The first wiring has low hydrogen permeability. The hydrogen permeability of the second insulator is lower than the hydrogen permeability of the first insulator.

公开(公告)号：US20180197889A1

公开(公告)日：2018-07-12

申请号：US15911233

申请日：2018-03-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Yuto Yakubo ,  Shuhei Nagatsuka

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H01L23/544

CPC classification number: H01L27/1225 ,  H01L23/544 ,  H01L27/1207 ,  H01L27/1259 ,  H01L29/66969 ,  H01L29/7869 ,  H01L2223/54453

Abstract: To provide a semiconductor device that is not easily damaged by ESD in a manufacturing process thereof. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided to overlap with a dicing line. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided around the semiconductor device such as a transistor. The layer may be in a floating state or may be supplied with a specific potential.

公开(公告)号：US09825037B2

公开(公告)日：2017-11-21

申请号：US15359873

申请日：2016-11-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki Inoue ,  Kiyoshi Kato ,  Takanori Matsuzaki ,  Shuhei Nagatsuka

IPC: G11C5/06 ,  H01L27/105 ,  G11C11/404 ,  G11C11/405 ,  G11C16/04 ,  H01L27/11521 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/108 ,  G11C16/08 ,  G11C16/24 ,  H01L29/786 ,  H01L21/02 ,  H01L21/425 ,  H01L21/441 ,  H01L21/477 ,  H01L27/11526 ,  H01L29/66 ,  G11C11/4091

CPC classification number: H01L27/1052 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4091 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/24 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/425 ,  H01L21/441 ,  H01L21/477 ,  H01L27/108 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/66969 ,  H01L29/78651 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.

公开(公告)号：US09685500B2

公开(公告)日：2017-06-20

申请号：US14645566

申请日：2015-03-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Yutaka Shionoiri ,  Tomoaki Atsumi ,  Shuhei Nagatsuka ,  Yutaka Okazaki ,  Suguru Hondo

IPC: H01L29/12 ,  H01L29/04 ,  H01L27/12 ,  H01L29/786 ,  H01L29/24 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/06

CPC classification number: H01L29/045 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device with a transistor having favorable electrical characteristics is provided. The semiconductor device has a memory circuit and a circuit that are over the same substrate. The memory circuit includes a capacitor, a first transistor, and a second transistor. A gate of the first transistor is electrically connected to the capacitor and one of a source and a drain of the second transistor. The circuit includes a third transistor and a fourth transistor that are electrically connected to each other in series. The first transistor and the third transistor each include an active layer including silicon, and the second transistor and the fourth transistor each include an active layer including an oxide semiconductor.

公开(公告)号：US09673224B2

公开(公告)日：2017-06-06

申请号：US14515993

申请日：2014-10-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Shuhei Nagatsuka ,  Tatsuya Onuki ,  Yutaka Shionoiri ,  Kiyoshi Kato ,  Hidekazu Miyairi

IPC: H01L27/12 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L29/42384 ,  H01L29/7869 ,  H01L29/78696

Abstract: To provide a semiconductor device that is suitable for miniaturization. The semiconductor device includes a first transistor, a second transistor over the first transistor, a barrier layer between the first transistor and the second transistor, a first electrode between the first transistor and the barrier layer, and a second electrode between the hairier layer and the second transistor and overlapping the first electrode with the barrier layer therebetween. A gate electrode of the first transistor, the first electrode, one of a source electrode and a drain electrode of the second transistor are electrically connected to one another. A channel is formed in a first semiconductor layer including a single crystal semiconductor in the first transistor. A channel is formed in a second semiconductor layer including an oxide semiconductor in the second transistor.

公开(公告)号：US09589611B2

公开(公告)日：2017-03-07

申请号：US15083776

申请日：2016-03-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko Ishizu ,  Shuhei Nagatsuka

IPC: G11C11/40 ,  G11C7/12 ,  H01L27/105 ,  H01L27/12 ,  H01L27/092 ,  H01L29/786 ,  G11C5/06 ,  G11C7/06

CPC classification number: G11C7/065 ,  G11C5/025 ,  G11C5/06 ,  G11C5/063 ,  G11C7/06 ,  G11C7/12 ,  G11C7/18 ,  G11C8/14 ,  G11C8/16 ,  G11C11/403 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/1108 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/1255 ,  H01L29/7869 ,  H01L29/78696

Abstract: A column driver includes an amplifier circuit for amplifying data of a read bit line and a latch circuit for retaining the amplified data. The latch circuit includes a pair of nodes Q and QB for retaining complementary data. Data is read from a memory cell in each write target row to a read bit line, and amplified by the amplifier circuit. The amplified data is written to the node Q (or QB) of the latch circuit. In a write target column, write data is input to the latch circuit through the node Q (or QB) to update data of the latch circuit. Then, in each column, data of the latch circuit is written to a write bit line, and the data of the write bit line is written to the memory cell.

Abstract translation: 列驱动器包括用于放大读位线的数据的放大器电路和用于保持放大数据的锁存电路。 锁存电路包括用于保留补充数据的一对节点Q和QB。 数据从每个写目标行中的存储单元读取到读位线，并由放大器电路放大。 放大的数据被写入到锁存电路的节点Q（或QB）。 在写目标列中，通过节点Q（或QB）将写入数据输入到锁存电路，以更新锁存电路的数据。 然后，在各列中，将锁存电路的数据写入写入位线，写入位线的数据被写入存储单元。

公开(公告)号：US09299813B2

公开(公告)日：2016-03-29

申请号：US14552551

申请日：2014-11-25

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hiroki Inoue ,  Kiyoshi Kato ,  Takanori Matsuzaki ,  Shuhei Nagatsuka

IPC: G11C11/24 ,  H01L29/66 ,  G11C11/404 ,  G11C11/405 ,  G11C16/04 ,  H01L27/115 ,  H01L27/12 ,  H01L27/108 ,  G11C16/08 ,  G11C16/24 ,  H01L29/786 ,  H01L21/02 ,  H01L21/425 ,  H01L21/441 ,  H01L21/477 ,  G11C11/4091

CPC classification number: H01L27/1052 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4091 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/24 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/425 ,  H01L21/441 ,  H01L21/477 ,  H01L27/108 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/66969 ,  H01L29/78651 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.

公开(公告)号：US09171630B2

公开(公告)日：2015-10-27

申请号：US14201068

申请日：2014-03-07

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shuhei Nagatsuka ,  Hiroki Inoue ,  Takahiko Ishizu ,  Takanori Matsuzaki ,  Yutaka Shionoiri ,  Kiyoshi Kato

IPC: G11C16/24 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/24 ,  G11C11/5642 ,  G11C16/0433 ,  G11C16/08

Abstract: To read multilevel data from a memory cell having a transistor using silicon and a transistor using an oxide semiconductor, without switching a signal for reading the multilevel data in accordance with the number of the levels of the multilevel data. The electrical charge of a bit line is discharged, the potential of the bit line is charged via a transistor for writing data, and the potential of the bit line which is changed by the charging is read as multilevel data. With such a structure, the potential corresponding to data held in a gate of the transistor can be read by only one-time switching of a signal for reading data.

Abstract translation: 从具有使用硅的晶体管的存储单元和使用氧化物半导体的晶体管读取多电平数据，而不用根据多电平数据的电平数来切换用于读取多电平数据的信号。 放电位线的电荷，通过用于写入数据的晶体管对位线的电位进行充电，并且通过充电而改变的位线的电位被读取为多电平数据。 通过这样的结构，可以通过仅读取数据的信号的一次切换来读取对应于保持在晶体管的栅极中的数据的电位。

公开(公告)号：US08988152B2

公开(公告)日：2015-03-24

申请号：US13768743

申请日：2013-02-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuro Ohmaru ,  Shuhei Nagatsuka

IPC: H03K3/03 ,  H01L29/786 ,  H01L27/088 ,  H01L27/12

CPC classification number: H01L29/786 ,  H01L27/088 ,  H01L27/1225 ,  H03K3/0315 ,  H03K19/0013 ,  H03K19/20 ,  H03K2005/00032 ,  H03K2005/00195 ,  H03K2217/0018

Abstract: To provide a semiconductor device including an inverter circuit whose driving frequency is increased by control of the threshold voltage of a transistor or a semiconductor device including an inveter circuit with low power consumption. An inverter circuit includes a first transistor and a second transistor each including a semiconductor film in which a channel is formed, a pair of gate electrodes between which the semiconductor film is placed, and source and drain electrodes in contact with the semiconductor film. Controlling potentials applied to the pair of gate electrodes makes the first transistor have normally-on characteristics and the second transistor have normally-off characteristics. Thus, the driving frequency of the inverter circuit is increased.

Abstract translation: 为了提供一种半导体器件，其包括通过控制晶体管的阈值电压或包括具有低功耗的入侵电路的半导体器件来驱动驱动频率的逆变器电路。 逆变器电路包括第一晶体管和第二晶体管，每个晶体管和第二晶体管都包括其中形成沟道的半导体膜，放置半导体膜的一对栅极电极和与半导体膜接触的源极和漏极。 施加到一对栅电极的控制电位使得第一晶体管具有常开特性，而第二晶体管具有常关特性。 因此，逆变器电路的驱动频率增加。