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323 条记录 (耗时 0.031 秒)

    Robust replacement gate integration
    64.
    发明授权
    Robust replacement gate integration 有权
    强大的替换门集成

    公开(公告)号：US09054127B2

    公开(公告)日：2015-06-09

    申请号：US14333555

    申请日：2014-07-17

    申请人： International Business Machines Corporation

    发明人： Hemanth Jagannathan ,  Sanjay Mehta

    IPC分类号： H01L29/76 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

    CPC分类号： H01L29/66545 ,  H01L29/49 ,  H01L29/66795 ,  H01L29/785

    摘要： A method including forming a dummy gate on a substrate, wherein the dummy gate includes an oxide, forming a pair of dielectric spacers on opposite sides of the dummy gate, and forming an inter-gate region above the substrate and in contact with at least one of the pair of dielectric spacers, the inter-gate region comprising a protective layer on top of a first oxide layer, wherein the protective layer comprises a material resistant to etching techniques designed to remove oxide. The method may further include removing the dummy gate to leave an opening, and forming a gate within the opening.

    摘要翻译： 一种包括在基板上形成虚拟栅极的方法，其中所述伪栅极包括氧化物，在所述伪栅极的相对侧上形成一对电介质间隔物，以及在所述基板上形成栅极间区域并与至少一个 所述栅极间区域包括在第一氧化物层的顶部上的保护层，其中所述保护层包括耐蚀刻技术以防止氧化物的材料。 该方法还可以包括去除虚拟门以留下开口，并且在开口内形成门。

    Non-volatile memory device employing semiconductor nanoparticles
    65.
    发明授权
    Non-volatile memory device employing semiconductor nanoparticles 有权
    采用半导体纳米颗粒的非易失性存储器件

    公开(公告)号：US08994006B2

    公开(公告)日：2015-03-31

    申请号：US13633347

    申请日：2012-10-02

    申请人： International Business Machines Corporation

    发明人： Kangguo Cheng ,  Robert H. Dennard ,  Hemanth Jagannathan ,  Ali Khakifirooz ,  Tak H. Ning ,  Ghavam G. Shahidi

    IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L27/115

    CPC分类号： H01L21/76251 ,  B82Y10/00 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11536 ,  H01L27/11543 ,  H01L27/11563 ,  H01L27/1203 ,  H01L29/66825 ,  H01L29/7881

    摘要： Semiconductor nanoparticles are deposited on a top surface of a first insulator layer of a substrate. A second insulator layer is deposited over the semiconductor nanoparticles and the first insulator layer. A semiconductor layer is then bonded to the second insulator layer to provide a semiconductor-on-insulator substrate, which includes a buried insulator layer including the first and second insulator layers and embedded semiconductor nanoparticles therein. Back gate electrodes are formed underneath the buried insulator layer, and shallow trench isolation structures are formed to isolate the back gate electrodes. Field effect transistors are formed in a memory device region and a logic device region employing same processing steps. The embedded nanoparticles can be employed as a charge storage element of non-volatile memory devices, in which charge carriers tunnel through the second insulator layer into or out of the semiconductor nanoparticles during writing and erasing.

    摘要翻译： 半导体纳米颗粒沉积在衬底的第一绝缘体层的顶表面上。 在半导体纳米颗粒和第一绝缘体层上沉积第二绝缘体层。 然后将半导体层接合到第二绝缘体层以提供绝缘体上半导体衬底，其包括在其中包括第一和第二绝缘体层的埋入式绝缘体层和嵌入的半导体纳米颗粒。 背栅电极形成在掩埋绝缘体层的下面，形成浅沟槽隔离结构以隔离背栅电极。 在存储器件区域和采用相同处理步骤的逻辑器件区域中形成场效应晶体管。 嵌入式纳米颗粒可以用作非易失性存储器件的电荷存储元件，其中电荷载体在写入和擦除期间穿过第二绝缘体层进入或流出半导体纳米颗粒。

    High performance non-planar semiconductor devices with metal filled inter-fin gaps
    66.
    发明授权
    High performance non-planar semiconductor devices with metal filled inter-fin gaps 有权
    具有金属填充的间隙间隙的高性能非平面半导体器件

    公开(公告)号：US08901667B2

    公开(公告)日：2014-12-02

    申请号：US14073366

    申请日：2013-11-06

    申请人： International Business Machines Corporation

    发明人： Hemanth Jagannathan ,  Sivananda Kanakasabapathy

    IPC分类号： H01L29/76 ,  H01L29/78 ,  H01L27/092

    CPC分类号： H01L27/0924 ,  H01L29/7845 ,  H01L29/785

    摘要： A non-planar semiconductor transistor device includes a substrate layer. Conductive channels extend between corresponding source and drain electrodes. A gate stack extending in a direction perpendicular to the conductive channels crosses over the plurality of conductive channels. The gate stack includes a dielectric layer running along the substrate and the plurality of conductive channels and arranged with a substantially uniform layer thickness, a work-function electrode layer covers the dielectric layer and is arranged with a substantially uniform layer thickness, and a metal layer, distinct from the work-function electrode layer, covers the work-function electrode layer and is arranged with a substantially uniform height with respect to the substrate such that the metal layer fills a gap between proximate conductive channels of the plurality of conductive channels.

    摘要翻译： 非平面半导体晶体管器件包括衬底层。 导电通道在相应的源极和漏极之间延伸。 沿垂直于导电通道的方向延伸的栅极堆叠跨过多个导电沟道。 栅极堆叠包括沿着衬底和多个导电沟道延伸并且布置成基本均匀的层厚度的电介质层，功函电极层覆盖电介质层并且布置成基本上均匀的层厚度，并且金属层 与工作功能电极层不同的是覆盖功函电极层，并且相对于衬底布置有基本均匀的高度，使得金属层填充多个导电沟道的邻近导电沟道之间的间隙。

    ROBUST REPLACEMENT GATE INTEGRATION
    67.
    发明申请
    ROBUST REPLACEMENT GATE INTEGRATION 有权

    公开(公告)号：US20140327076A1

    公开(公告)日：2014-11-06

    申请号：US14333555

    申请日：2014-07-17

    申请人： International Business Machines Corporation

    发明人： Hemanth Jagannathan ,  Sanjay Mehta

    IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/49

    CPC分类号： H01L29/66545 ,  H01L29/49 ,  H01L29/66795 ,  H01L29/785

    摘要： A method including forming a dummy gate on a substrate, wherein the dummy gate includes an oxide, forming a pair of dielectric spacers on opposite sides of the dummy gate, and forming an inter-gate region above the substrate and in contact with at least one of the pair of dielectric spacers, the inter-gate region comprising a protective layer on top of a first oxide layer, wherein the protective layer comprises a material resistant to etching techniques designed to remove oxide. The method may further include removing the dummy gate to leave an opening, and forming a gate within the opening.

    ROBUST REPLACEMENT GATE INTEGRATION
    68.
    发明申请
    ROBUST REPLACEMENT GATE INTEGRATION 有权
    稳健的替代门槛整合

    公开(公告)号：US20140124873A1

    公开(公告)日：2014-05-08

    申请号：US13670748

    申请日：2012-11-07

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Hemanth Jagannathan ,  Sanjay Mehta

    IPC分类号： H01L29/423 ,  H01L21/28

    CPC分类号： H01L29/66545 ,  H01L29/49 ,  H01L29/66795 ,  H01L29/785

    摘要： A method including forming a dummy gate on a substrate, wherein the dummy gate includes an oxide, forming a pair of dielectric spacers on opposite sides of the dummy gate, and forming an inter-gate region above the substrate and in contact with at least one of the pair of dielectric spacers, the inter-gate region comprising a protective layer on top of a first oxide layer, wherein the protective layer comprises a material resistant to etching techniques designed to remove oxide. The method may further include removing the dummy gate to leave an opening, and forming a gate within the opening.

    摘要翻译： 一种包括在基板上形成虚拟栅极的方法，其中所述伪栅极包括氧化物，在所述伪栅极的相对侧上形成一对电介质间隔物，以及在所述基板上形成栅极间区域并与至少一个 所述栅极间区域包括在第一氧化物层的顶部上的保护层，其中所述保护层包括耐蚀刻技术以防止氧化物的材料。 该方法还可以包括去除虚拟门以留下开口，并且在开口内形成门。

    REPLACEMENT GATE WITH REDUCED GATE LEAKAGE CURRENT
    69.
    发明申请
    REPLACEMENT GATE WITH REDUCED GATE LEAKAGE CURRENT 审中-公开
    具有降低闸门泄漏电流的更换门

    公开(公告)号：US20130260549A1

    公开(公告)日：2013-10-03

    申请号：US13771937

    申请日：2013-02-20

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Hemanth Jagannathan ,  Ramachandra Divakaruni ,  Unoh Kwon ,  Vijay Narayanan ,  Ravikumar Ramachandran

    IPC分类号： H01L21/285

    CPC分类号： H01L21/28518 ,  H01L21/26506 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/105 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

    摘要： Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material, which provides, in combination with other layer, a work function about 4.4 eV or less, and can include a material selected from tantalum carbide, metallic nitrides, and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel. Optionally, carbon doping can be introduced in the channel.

    摘要翻译： 提供了替代栅极工作功能材料堆叠，其提供关于硅导带的能级的功函数。 在去除一次性栅极堆叠之后，在栅极腔中形成栅极电介质层。 包括金属和非金属元素的金属化合物层直接沉积在栅极介电层上。 沉积至少一个势垒层和导电材料层并平坦化以填充栅极腔。 金属化合物层包括与其它层组合提供约4.4eV或更低的功函数的材料，并且可以包括选自碳化钽，金属氮化物和铪硅合金的材料。 因此，金属化合物层可以提供增强采用硅通道的n型场效应晶体管的性能的功函数。 任选地，可以在通道中引入碳掺杂。