公开(公告)号：US20150140732A1

公开(公告)日：2015-05-21

申请号：US14578891

申请日：2014-12-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Mitsuhiro ICHIJO ,  Tetsuhiro TANAKA ,  Seiji YASUMOTO ,  Shun MASHIRO ,  Yoshiaki OIKAWA ,  Kenichi OKAZAKI

IPC: H01L21/02 ,  H01L29/66

CPC classification number: H01L21/44 ,  C23C16/308 ,  C23C16/45578 ,  C23C16/511 ,  H01J37/32192 ,  H01J37/3244 ,  H01J37/32449 ,  H01J37/34 ,  H01L21/02274 ,  H01L21/0237 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02614 ,  H01L21/02631 ,  H01L21/67167 ,  H01L29/24 ,  H01L29/42356 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/7869

Abstract: It is an object to drive a semiconductor device at high speed or to improve the reliability of the semiconductor device. In a method for manufacturing the semiconductor device, in which a gate electrode is formed over a substrate with an insulating property, a gate insulating film is formed over the gate electrode, and an oxide semiconductor film is formed over the gate insulating film, the gate insulating film is formed by deposition treatment using high-density plasma. Accordingly, dangling bonds in the gate insulating film are reduced and the quality of the interface between the gate insulating film and the oxide semiconductor is improved.

Abstract translation: 本发明的目的是高速驱动半导体器件或提高半导体器件的可靠性。 在半导体器件的制造方法中，其中在绝缘性的衬底上形成栅电极，在栅电极上形成栅极绝缘膜，并且在栅极绝缘膜上形成氧化物半导体膜，栅极 通过使用高密度等离子体的沉积处理形成绝缘膜。 因此，栅极绝缘膜中的悬挂键减少，并且栅极绝缘膜和氧化物半导体之间的界面的质量得到改善。

公开(公告)号：US20150069387A1

公开(公告)日：2015-03-12

申请号：US14479623

申请日：2014-09-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshitaka YAMAMOTO ,  Tetsuhiro TANAKA ,  Takayuki INOUE ,  Hideomi SUZAWA ,  Yasuhiko TAKEMURA

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  G11C11/24 ,  G11C16/00 ,  G11C16/0466 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78648 ,  H01L29/78696 ,  H01L29/7881

Abstract: A method for manufacturing a semiconductor device with adjusted threshold is provided. In a semiconductor device including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a first gate electrode and a second gate electrode between which the semiconductor is provided, a charge trap layer provided between the first gate electrode and the semiconductor, and a gate insulating layer provided between the second gate electrode and the semiconductor, a threshold is increased by trapping electrons in the charge trap layer by keeping a potential of the first gate electrode at a potential higher than a potential of the source or drain electrode for 1 second or more while heating. After the threshold adjustment process, the first gate electrode is removed or insulated from other circuits. Alternatively, a resistor may be provided between the first gate electrode and other circuits.

Abstract translation: 提供一种用于制造具有调节阈值的半导体器件的方法。 在包括半导体，与半导体电连接的源电极或漏电极的半导体器件中，设置有半导体的第一栅电极和第二栅电极，设置在第一栅电极和半导体之间的电荷陷阱层，以及 设置在第二栅电极和半导体之间的栅极绝缘层，通过将第一栅电极的电位保持在高于源电极或漏电极的电位的电位为1，通过在电荷陷阱层中俘获电子来增加阈值 第二次或多次加热。 在阈值调整处理之后，第一栅电极被去除或与其它电路绝缘。 或者，可以在第一栅极电极和其它电路之间设置电阻器。

公开(公告)号：US20150054548A1

公开(公告)日：2015-02-26

申请号：US14464966

申请日：2014-08-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi KATO ,  Yasuhiko TAKEMURA ,  Tetsuhiro TANAKA ,  Takayuki INOUE ,  Toshihiko TAKEUCHI ,  Yasumasa YAMANE ,  Shunpei YAMAZAKI

IPC: H03K19/00 ,  H01L21/324 ,  H01L27/115 ,  H03K19/003 ,  H01L29/792

CPC classification number: H01L29/792 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/1225 ,  H01L29/4234 ,  H01L29/66833 ,  H03K19/0013 ,  H03K19/17736

Abstract: A manufacturing method of a semiconductor device in which the threshold is adjusted is provided. In a semiconductor device including a plurality of transistors arranged in a matrix each including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and a charge trap layer between the gate electrode and the semiconductor, electrons are trapped in the charge trap layer by performing heat treatment and, simultaneously, keeping a potential of the gate electrode higher than that of the source or drain electrode for 1 second or more. By this process, the threshold increases and Icut decreases. A circuit that supplies a signal to the gate electrode (e.g., word line driver) is provided with a selection circuit formed of an OR gate, an XOR gate, or the like, whereby potentials of word lines can be simultaneously set higher than potentials of bit lines.

Abstract translation: 提供了其中调整阈值的半导体器件的制造方法。 在包括以矩阵形式排列的多个晶体管的半导体器件中，每个晶体管包括半导体，与该半导体电连接的源极或漏极，栅电极和栅电极与半导体之间的电荷陷阱层，电子被俘获在 通过进行热处理，同时使栅电极的电位比源极或漏极的电位高1秒以上。 通过该过程，阈值增加并且Icut减小。 向门电极（例如字线驱动器）提供信号的电路设置有由或门，异或门等形成的选择电路，由此可以将字线的电位同时设置为高于电位 位线。

公开(公告)号：US20140239293A1

公开(公告)日：2014-08-28

申请号：US14174438

申请日：2014-02-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Akihisa SHIMOMURA ,  Tetsuhiro TANAKA ,  Sachiaki TEZUKA

IPC: H01L29/78 ,  H01L29/26

CPC classification number: H01L29/7869 ,  H01L29/105 ,  H01L29/26 ,  H01L29/41733 ,  H01L29/78 ,  H01L29/78693 ,  H01L29/78696

Abstract: Disclosed is a semiconductor device including two oxide semiconductor layers, where one of the oxide semiconductor layers has an n-doped region while the other of the oxide semiconductor layers is substantially i-type. The semiconductor device includes the two oxide semiconductor layers sandwiched between a pair of oxide layers which have a common element included in any of the two oxide semiconductor layers. A double-well structure is formed in a region including the two oxide semiconductor layers and the pair of oxide layers, leading to the formation of a channel formation region in the n-doped region. This structure allows the channel formation region to be surrounded by an i-type oxide semiconductor, which contributes to the production of a semiconductor device that is capable of feeding enormous current.

Abstract translation: 公开了包括两个氧化物半导体层的半导体器件，其中氧化物半导体层中的一个具有n掺杂区域，而另一个氧化物半导体层基本上是i型。 半导体器件包括夹在一对氧化物层之间的两个氧化物半导体层，其具有包含在两个氧化物半导体层中的任一个中的共同元素。 在包括两个氧化物半导体层和一对氧化物层的区域中形成双阱结构，导致在n掺杂区域中形成沟道形成区域。 该结构允许沟道形成区域被i型氧化物半导体包围，这有助于生产能够馈送大量电流的半导体器件。

公开(公告)号：US20140106504A1

公开(公告)日：2014-04-17

申请号：US14054162

申请日：2013-10-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Tetsuhiro TANAKA

IPC: H01L21/02 ,  H01L29/26 ,  H01L29/78 ,  H01L29/04

CPC classification number: H01L21/02565 ,  C23C14/086 ,  C23C14/3414 ,  H01L21/02488 ,  H01L21/02554 ,  H01L21/02592 ,  H01L21/02609 ,  H01L21/02617 ,  H01L21/02631 ,  H01L21/441 ,  H01L21/47576 ,  H01L21/47635 ,  H01L29/045 ,  H01L29/26 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/7869

Abstract: To provide a semiconductor device in which an increase in oxygen vacancies is suppressed. To provide a semiconductor device with favorable electrical characteristics. To provide a highly reliable semiconductor device. In a semiconductor device in which a channel formation region is included in an oxide semiconductor layer, an oxide insulating film below and in contact with the oxide semiconductor layer and a gate insulating film over and in contact with the oxide semiconductor layer are used to supply oxygen of the gate insulating film, which is introduced by an ion implantation method, to the oxide semiconductor layer.

Abstract translation: 提供抑制氧空位增加的半导体器件。 提供具有良好电特性的半导体器件。 提供高度可靠的半导体器件。 在氧化物半导体层中包括沟道形成区域的半导体器件中，使用氧化物半导体层下方并与氧化物半导体层接触的氧化物绝缘膜和与氧化物半导体层接触并与氧化物半导体层接触的栅极绝缘膜供给氧 通过离子注入法引入的栅极绝缘膜到氧化物半导体层。

公开(公告)号：US20130285051A1

公开(公告)日：2013-10-31

申请号：US13870370

申请日：2013-04-25

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tetsuhiro TANAKA

IPC: H01L29/66 ,  H01L29/786

CPC classification number: H01L29/66742 ,  H01L27/1225 ,  H01L29/78642 ,  H01L29/7869

Abstract: Miniaturized transistors having high and stable electric characteristics using high precision microfabrication are provided with high yield. Further, high performance, high reliability, and high productivity also of a semiconductor device including the transistor are achieved. A semiconductor device includes a vertical transistor in which a first electrode layer, a first oxide film containing indium, gallium, zinc, and nitrogen as main components, an oxide semiconductor film containing indium, gallium, and zinc as main components, a second oxide film containing indium, gallium, zinc, and nitrogen as main components, and a second electrode layer are stacked in this order, and a first gate insulating film and a first gate electrode layer are provided at one side of the columnar oxide semiconductor film and a second gate insulating film and a second gate electrode layer are provided at the other side of the columnar oxide semiconductor film.

Abstract translation: 具有高精度微细加工的高稳定电特性的小型化晶体管以高产率被提供。 此外，实现了包括晶体管的半导体器件的高性能，高可靠性和高生产率。 半导体器件包括垂直晶体管，其中第一电极层，包含铟，镓，锌和氮作为主要成分的第一氧化物膜，以铟，镓和锌为主要成分的氧化物半导体膜，第二氧化物膜 含有铟，镓，锌和氮作为主要成分，第二电极层依次层叠，第一栅极绝缘膜和第一栅电极层设置在柱状氧化物半导体膜的一侧， 栅极绝缘膜和第二栅电极层设置在柱状氧化物半导体膜的另一侧。

公开(公告)号：US20130140555A1

公开(公告)日：2013-06-06

申请号：US13686332

申请日：2012-11-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Motomu KURATA ,  Shinya SASAGAWA ,  Taiga MURAOKA ,  Tetsuhiro TANAKA ,  Junichi KOEZUKA

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/66742 ,  H01L29/66969

Abstract: Provided is a miniaturized transistor with stable and high electrical characteristics with high yield. In a semiconductor device including the transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode layer are stacked in this order, a first sidewall insulating layer is provided in contact with a side surface of the gate electrode layer, and a second sidewall insulating layer is provided to cover a side surface of the first sidewall insulating layer. The first sidewall insulating layer is an aluminum oxide film in which a crevice with an even shape is formed on its side surface. The second sidewall insulating layer is provided to cover the crevice. A source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor film and the second sidewall insulating layer.

公开(公告)号：US20250063762A1

公开(公告)日：2025-02-20

申请号：US18936334

申请日：2024-11-04

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Tetsuhiro TANAKA ,  Hirokazu WATANABE ,  Yuhei SATO ,  Yasumasa YAMANE ,  Daisuke MATSUBAYASHI

IPC: H01L29/786 ,  H01L29/45 ,  H01L29/66

Abstract: A semiconductor device having a reduced amount of oxygen vacancy in a channel formation region of an oxide semiconductor is provided. Further, a semiconductor device which includes an oxide semiconductor and has improved electric characteristics is provided. Furthermore, a methods for manufacturing the semiconductor device is provided. An oxide semiconductor film is formed; a conductive film is formed over the oxide semiconductor film at the same time as forming a low-resistance region between the oxide semiconductor film and the conductive film; the conductive film is processed to form a source electrode and a drain electrode; and oxygen is added to the low-resistance region between the source electrode and the drain electrode, so that a channel formation region having a higher resistance than the low-resistance region is formed and a first low-resistance region and a second low-resistance region between which the channel formation region is positioned are formed.

公开(公告)号：US20240128380A1

公开(公告)日：2024-04-18

申请号：US18526315

申请日：2023-12-01

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yutaka OKAZAKI ,  Akihisa SHIMOMURA ,  Naoto YAMADE ,  Tomoya TAKESHITA ,  Tetsuhiro TANAKA

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78609 ,  H01L29/78648 ,  H01L29/7869

Abstract: A transistor with favorable electrical characteristics is provided. One embodiment of the present invention is a semiconductor device including a semiconductor, a first insulator in contact with the semiconductor, a first conductor in contact with the first insulator and overlapping with the semiconductor with the first insulator positioned between the semiconductor and the first conductor, and a second conductor and a third conductor, which are in contact with the semiconductor. One or more of the first to third conductors include a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, and nickel.

公开(公告)号：US20240105713A1

公开(公告)日：2024-03-28

申请号：US18519200

申请日：2023-11-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tetsuhiro TANAKA ,  Yutaka OKAZAKI

IPC: H01L27/07 ,  H01G4/008 ,  H01G4/10 ,  H01G4/40 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H01L29/94 ,  H05K1/18

CPC classification number: H01L27/0733 ,  H01G4/008 ,  H01G4/105 ,  H01G4/40 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/66477 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696 ,  H01L29/94 ,  H05K1/18 ,  H01L21/8258

Abstract: A miniaturized transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a large amount of on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device with high integration is provided. A novel capacitor is provided. The capacitor includes a first conductor, a second conductor, and an insulator. The first conductor includes a region overlapping with the second conductor with the insulator provided therebetween. The first conductor includes tungsten and silicon. The insulator includes a silicon oxide film that is formed by oxidizing the first conductor.