公开(公告)号：US07091600B2

公开(公告)日：2006-08-15

申请号：US10791014

申请日：2004-03-02

Applicant: Chung-Shi Liu ,  Shau-Lin Shue

Inventor： Chung-Shi Liu ,  Shau-Lin Shue

IPC: H01L23/48

CPC classification number: H01L21/76829 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/7684 ,  H01L21/76877

Abstract: A common problem associated with damascene structures made of copper inlaid in FSG (fluorinated silicate glass) is the formation of defects near the top surface of the structure. The present invention avoids this problem by laying down a layer of USG (undoped silicate glass) over the surface of the FSG layer prior to patterning and etching the latter to form the via hole and (for a dual damascene structure) the trench. After over-filling with copper, the structure is planarized using CMP. The USG layer acts both to prevent any fluorine from the FSG layer from reaching the copper and as an end-point detector during CMP. In this way defects that result from copper-fluorine interaction do not form and precise planarization is achieved.

Abstract translation: 与镶嵌在FSG（氟化硅酸盐玻璃）中的铜构成的镶嵌结构相关的常见问题是在结构顶表面附近形成缺陷。 本发明通过在图案化之前放置一层USG（未掺杂的硅酸盐玻璃）以避免这种问题，然后在图案化之前对其进行蚀刻，以形成通孔和（用于双镶嵌结构）沟槽。 用铜填充后，使用CMP对结构进行平面化处理。 USG层既可以防止FSG层中的任何氟达到铜，也可以作为CMP中的终点检测器。 以这种方式，铜 - 氟相互作用产生的缺陷不能形成并且实现精确的平坦化。

公开(公告)号：US20060027922A1

公开(公告)日：2006-02-09

申请号：US10909980

申请日：2004-08-03

Applicant: Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ching-Hua Hsieh ,  Chao-Hsien Peng ,  Cheng-Lin Huang ,  Li-Lin Su ,  Shau-Lin Shue

Inventor： Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ching-Hua Hsieh ,  Chao-Hsien Peng ,  Cheng-Lin Huang ,  Li-Lin Su ,  Shau-Lin Shue

IPC: H01L23/48

CPC classification number: H01L21/76834 ,  H01L21/76849 ,  H01L21/76867 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having a nonconductive cap layer comprising a first metal element. The nonconductive cap layer comprises a first metal nitride, a first metal oxide, or a first metal oxynitride over conductive lines and an insulating material between the conductive lines. An interface region may be formed over the top surface of the conductive lines, the interface region including the metal element of the cap layer. The cap layer prevents the conductive material in the conductive lines from migrating or diffusing into adjacent subsequently formed insulating material layers. The cap layer may also function as an etch stop layer.

Abstract translation: 一种具有包括第一金属元件的非导电盖层的半导体器件。 非导电盖层包括导电线上的第一金属氮化物，第一金属氧化物或第一金属氧氮化物，以及导电线之间的绝缘材料。 界面区域可以形成在导电线的顶表面上，界面区域包括盖层的金属元件。 盖层防止导电线中的导电材料迁移或扩散到相邻的随后形成的绝缘材料层中。 盖层也可以用作蚀刻停止层。

公开(公告)号：US20050272235A1

公开(公告)日：2005-12-08

申请号：US10859730

申请日：2004-06-03

Applicant: Chii-Ming Wu ,  Cheng-Tung Lin ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

Inventor： Chii-Ming Wu ,  Cheng-Tung Lin ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/4763 ,  H01L29/49

CPC classification number: H01L21/28097 ,  H01L21/28518 ,  H01L29/4975 ,  H01L29/66507 ,  H01L29/785

Abstract: A method of forming a silicided gate of a field effect transistor on a substrate having active regions is provided. The method includes the following steps: (a) forming a silicide in at least a first portion of a gate; (b) after step (a), depositing a metal over the active regions and said gate; and (c) annealing to cause the metal to react to form silicide in the active regions, wherein the thickness of said gate silicide is greater than the thickness of said silicide in said active regions.

Abstract translation: 提供了在具有有源区的基板上形成场效应晶体管的硅化物栅的方法。 该方法包括以下步骤：（a）在栅极的至少第一部分中形成硅化物; （b）在步骤（a）之后，在有源区域和所述栅极上沉积金属; 和（c）退火以引起金属反应以在有源区中形成硅化物，其中所述栅极硅化物的厚度大于所述有源区中所述硅化物的厚度。

公开(公告)号：US20050260851A1

公开(公告)日：2005-11-24

申请号：US10850763

申请日：2004-05-20

Applicant: Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

Inventor： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

IPC: H01L21/285 ,  H01L21/306 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76865 ,  H01L21/02046 ,  H01L21/2855 ,  H01L21/32131 ,  H01L21/76843 ,  H01L21/76862

Abstract: A novel process for re-distributing a barrier layer deposited on a single damascene, dual damascene or other contact opening structure. The process includes providing a substrate having a contact opening structure and a metal barrier layer deposited in the contact opening structure, re-sputtering the barrier layer by bombarding the barrier layer with argon ions and metal ions, and re-sputtering the barrier layer by bombarding the barrier layer with argon ions.

Abstract translation: 一种用于重新分布沉积在单个镶嵌，双镶嵌或其他接触开口结构上的阻挡层的新方法。 该方法包括提供具有接触开口结构的衬底和沉积在接触开口结构中的金属阻挡层，通过用氩离子和金属离子轰击阻挡层来重新溅射阻挡层，并通过轰击来重新溅射阻挡层 阻挡层具有氩离子。

公开(公告)号：US20050158986A1

公开(公告)日：2005-07-21

申请号：US11052938

申请日：2005-02-07

Applicant: Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue ,  Ju-Wang Hsu ,  Ming-Huan Tsai

Inventor： Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue ,  Ju-Wang Hsu ,  Ming-Huan Tsai

IPC: H01L21/311 ,  H01L21/60 ,  H01L21/768 ,  H01L21/20 ,  H01L21/4763

CPC classification number: H01L21/76829 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76832

Abstract: A method of manufacturing a semiconductor device is provided comprising the steps of: (a) forming a semiconductor element on a substrate, the semiconductor element having at least one nickel silicide contact region, a first etch stop layer formed over the element and an insulating layer formed over the first etch stop layer; (b) forming an opening through the insulating layer over the contact region at least to the first etch stop layer; (c) removing a portion of the first etch stop layer contacting a selected contact region using a process that does not substantially oxidize with the contact region, to form a contact opening to the contact region; and (d) filling the contact opening with conductive material to form a contact.

Abstract translation: 提供一种制造半导体器件的方法，包括以下步骤：（a）在衬底上形成半导体元件，所述半导体元件具有至少一个硅化镍接触区域，形成在元件上的第一蚀刻停止层和绝缘层 形成在第一蚀刻停止层上; （b）至少在所述第一蚀刻停止层上在所述接触区域上形成穿过所述绝缘层的开口; （c）使用不与接触区域基本上氧化的工艺去除与所选择的接触区域接触的第一蚀刻停止层的一部分，以形成到接触区域的接触开口; 和（d）用导电材料填充接触开口以形成接触。

公开(公告)号：US20050092598A1

公开(公告)日：2005-05-05

申请号：US10702970

申请日：2003-11-05

Applicant: Mei-Yun Wang ,  Chih-Wei Chang ,  Chii-Ming Wu ,  Cheng-Tung Lin ,  Shau-Lin Shue

Inventor： Mei-Yun Wang ,  Chih-Wei Chang ,  Chii-Ming Wu ,  Cheng-Tung Lin ,  Shau-Lin Shue

IPC: C23C14/16 ,  H01L21/285 ,  C23C16/00 ,  C23C14/32

CPC classification number: H01L21/28518 ,  C23C14/16

Abstract: A process for reducing the thermal budget and enhancing stability in the thermal budget of a metal salicide process used in the formation of metal salicides on substrates, thus eliminating or reducing salicide spiking and junction leakage in microelectronic devices fabricated on the substrates. According to a typical embodiment, a substrate is cooled to a sub-processing temperature which is lower than the metal deposition processing temperature and the salicide-forming metal is deposited onto the reduced-temperature substrate.

Abstract translation: 一种用于降低热预算并增强用于在基材上形成金属硅化物的金属硅化物工艺的热预算中的稳定性的方法，从而消除或减少在衬底上制造的微电子器件中的自杀剂尖峰和结漏电。 根据典型的实施方式，将基板冷却至比金属沉积处理温度低的副处理温度，并将形成自杀型化合物的金属沉积在还原温度基板上。

公开(公告)号：US20050054202A1

公开(公告)日：2005-03-10

申请号：US10655972

申请日：2003-09-04

Applicant: Shing-Chyang Pan ,  Ching-Hua Hsieh ,  Jing-Cheng Lin ,  Hsien-Ming Lee ,  Cheng-Lin Huang ,  Shau-Lin Shue

Inventor： Shing-Chyang Pan ,  Ching-Hua Hsieh ,  Jing-Cheng Lin ,  Hsien-Ming Lee ,  Cheng-Lin Huang ,  Shau-Lin Shue

IPC: H01L21/285 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/3105 ,  H01L21/28556 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76873

Abstract: A method for forming a copper damascene feature including providing a semiconductor process wafer including at least one via opening formed to extend through a thickness of at least one dielectric insulating layer and an overlying trench line opening encompassing the at least one via opening to form a dual damascene opening; etching through an etch stop layer at the at least one via opening bottom portion to expose an underlying copper area; carrying out a sub-atmospheric DEGAS process with simultaneous heating of the process wafer in a hydrogen containing ambient; carrying out an in-situ sputter-clean process; and, forming a barrier layer in-situ to line the dual damascene opening.

Abstract translation: 一种用于形成铜镶嵌特征的方法，包括提供半导体工艺晶片，其包括形成为延伸穿过至少一个介电绝缘层的厚度的至少一个通孔开口，以及覆盖所述至少一个通孔开口的上覆沟槽开口，以形成双重 大马士革开幕 在所述至少一个通孔开口底部处蚀刻通过蚀刻停止层以暴露下面的铜区域; 在含氢环境中同时加热工艺晶片，进行亚低温DEGAS工艺; 进行原位溅射清洗过程; 并且原位形成阻挡层以使双镶嵌开口成线。

公开(公告)号：US20050045092A1

公开(公告)日：2005-03-03

申请号：US10653852

申请日：2003-09-03

Applicant: Chii-Ming Wu ,  Chao-Hsien Peng ,  Shau-Lin Shue

Inventor： Chii-Ming Wu ,  Chao-Hsien Peng ,  Shau-Lin Shue

IPC: C30B25/02 ,  C30B25/14 ,  H01L21/314 ,  H01L21/316 ,  C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC classification number: H01L21/0228 ,  C30B25/02 ,  C30B25/14 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/3141 ,  H01L21/31641 ,  H01L21/31645

Abstract: An ALD method is described for depositing a composite layer comprised of three to five elements including one or two metals, Si, B and N. A metal containing gas is injected into a process chamber and purged followed by a N source gas and a purge and/or a Si or B source gas and a purge to complete a cycle and form a monolayer. A predetermined number of monolayers each having two or three elements is deposited to provide a composite film with good step coverage and a well controlled composition. The resulting layer is especially useful as a diffusion barrier layer for copper. Alternatively, a three component layer comprised of Hf, Zr, and O may be deposited and serves as a gate dielectric layer in a MOSFET device. The invention is also a thin film comprised of a plurality of monolayers each having two or three elements.

Abstract translation: 描述了一种ALD方法，用于沉积由包括一种或两种金属Si，B和N的三至五个元素组成的复合层。将含金属的气体注入到处理室中，然后吹扫N源气体和吹扫， /或Si或B源气体和吹扫以完成循环并形成单层。 沉积预定数量的具有两个或三个元素的单层，以提供具有良好的步骤覆盖率和良好控制的组合物的复合膜。 所得的层特别适用于铜的扩散阻挡层。 或者，可以沉积由Hf，Zr和O组成的三组分层，并且用作MOSFET器件中的栅介质层。 本发明也是由多个单层组成的薄膜，每个单层具有两个或三个元素。

公开(公告)号：US06759750B2

公开(公告)日：2004-07-06

申请号：US10623910

申请日：2003-07-18

Applicant: Shau-Lin Shue ,  Ming-Hsing Tsai

Inventor： Shau-Lin Shue ,  Ming-Hsing Tsai

IPC: H01L2348

CPC classification number: H01L23/522 ,  H01L21/76801 ,  H01L21/76807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for integrating low-K materials in semiconductor fabrication. The process begins by providing a semiconductor structure having a dielectric layer thereover, wherein the dielectric layer comprising an organic low-K material. The dielectric layer is patterned to form pillar openings. A pillar layer is deposited over the semiconductor structure; thereby filling the pillar openings with the pillar layer. The pillar layer is planarized to form pillars embedded in said dielectric layer. The pillar layer comprises a material having good thermal stability, good structural strength, and good bondability of spin coating back-end materials, improving the manufacturability of organic, low-K dielectrics in semiconductor fabrication. In one embodiment, the pillars are formed prior to forming dual damascene interlayer contacts. In another embodiment, pillars are formed simultaneously with interlayer contacts.

Abstract translation: 一种用于在半导体制造中集成低K材料的方法。 该方法开始于提供其上具有介电层的半导体结构，其中介电层包含有机低K材料。 图案化电介质层以形成柱状开口。 在半导体结构上沉积柱层; 从而用柱层填充柱状开口。 柱层被平坦化以形成嵌入在所述介电层中的柱。 柱层包括具有良好的热稳定性，良好的结构强度和旋涂后端材料的良好的粘合性的材料，提高半导体制造中的有机，低K电介质的可制造性。 在一个实施例中，在形成双镶嵌层间接触之前形成柱。 在另一个实施方案中，柱与层间接触同时形成。

公开(公告)号：US06686280B1

公开(公告)日：2004-02-03

申请号：US09989802

申请日：2001-11-20

Applicant: Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

Inventor： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

IPC: H01L2100

CPC classification number: H01L21/76843 ,  H01L21/2855 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76874 ,  H01L2221/1089

Abstract: A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the hole or trench by means of PVD. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. A number of process variations are described including double etch/deposit steps, varying pressure and voltage in the same chamber to allow sputter etching and deposition to take place without breaking vacuum, and reduction of contact resistance between wiring levels by reducing via depth.