公开(公告)号：US08106512B2

公开(公告)日：2012-01-31

申请号：US12845852

申请日：2010-07-29

申请人： Hsiang-Huan Lee ,  Ming Han Lee ,  Ming-Shih Yeh ,  Chen-Hua Yu ,  Shau-Lin Shue

发明人： Hsiang-Huan Lee ,  Ming Han Lee ,  Ming-Shih Yeh ,  Chen-Hua Yu ,  Shau-Lin Shue

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/53238 ,  H01L21/28562 ,  H01L21/76846 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76883 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： The structures and methods described above provide mechanisms to improve interconnect reliability and resistivity. The interconnect reliability and resistivity are improved by using a composite barrier layer, which provides good step coverage, good copper diffusion barrier, and good adhesion with adjacent layers. The composite barrier layer includes an ALD barrier layer to provide good step coverage. The composite barrier layer also includes a barrier-adhesion-enhancing film, which contains at least an element or compound that contains Mn, Cr, V, Ti, or Nb to improve adhesion. The composite barrier layer may also include a Ta or Ti layer between the ALD barrier layer and the barrier-adhesion-enhancing layer.

摘要翻译： 上述结构和方法提供了提高互连可靠性和电阻率的机制。 通过使用复合阻挡层来提高互连的可靠性和电阻率，该复合阻挡层提供良好的台阶覆盖率，良好的铜扩散阻挡层和与相邻层的良好粘附性。 复合阻挡层包括ALD阻挡层以提供良好的阶梯覆盖。 复合阻挡层还包括至少包含含有Mn，Cr，V，Ti或Nb的元素或化合物以提高粘合性的阻隔增粘膜。 复合阻挡层还可以包括在ALD阻挡层和阻挡增粘层之间的Ta或Ti层。

公开(公告)号：US20110259734A1

公开(公告)日：2011-10-27

申请号：US13176839

申请日：2011-07-06

申请人： Chung-Liang Chang ,  Shau-Lin Shue

发明人： Chung-Liang Chang ,  Shau-Lin Shue

IPC分类号： C25D7/12 ,  C25D17/06 ,  C25D17/10 ,  C25D17/02

CPC分类号： H01L21/2885 ,  C25D5/18 ,  C25D7/123 ,  C25D17/001 ,  C25D17/007 ,  H01L21/76877

摘要： An electroplating apparatus for depositing a conductive material on a semiconductor wafer includes a vessel for holding an electroplating bath, a support for holding a semiconductor wafer within the vessel and beneath a surface of the bath; first and second electrodes within the vessel, between which an electrical current may flow causing conductive material to be electrolytically deposited onto the wafer, a third electrode disposed outside of the bath for applying a static electric charge to the wafer, and an electrical power supply coupled with the third electrode.

摘要翻译： 用于在半导体晶片上沉积导电材料的电镀设备包括用于保持电镀槽的容器，用于将半导体晶片保持在容器内并在浴表面下方的支撑体; 容器内的第一和第二电极，电流可以在其间流动，导致导电材料被电解沉积到晶片上;第三电极，设置在电镀槽的外面，用于向晶片施加静电荷;以及电源， 与第三电极。

公开(公告)号：US20110241217A1

公开(公告)日：2011-10-06

申请号：US12750100

申请日：2010-03-30

申请人： Hung-Pin Chang ,  Chien-Ming Chiu ,  Tsang-Jiuh Wu ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Hung-Pin Chang ,  Chien-Ming Chiu ,  Tsang-Jiuh Wu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L21/6835 ,  H01L23/525 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/68359 ,  H01L2224/13022 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/14181 ,  H01L2924/01019 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements.

摘要翻译： 提供了用于堆叠管芯配置的多层互连结构。 在半导体衬底中形成贯通衬底通孔。 将半导体衬底的背面变薄以暴露通过衬底的通孔。 在半导体衬底的背面和贯通衬底通孔的暴露部分之后形成隔离膜。 第一导电元件被形成为电耦合到贯穿衬底通孔中的相应通孔并且在隔离膜上延伸。 可以形成一个或多个附加层的隔离膜和导电元件，其中诸如焊球的连接元件电耦合到最上面的导电元件。

公开(公告)号：US07988843B2

公开(公告)日：2011-08-02

申请号：US12705903

申请日：2010-02-15

申请人： Chung-Liang Chang ,  Shau-Lin Shue

发明人： Chung-Liang Chang ,  Shau-Lin Shue

IPC分类号： C25D5/34

CPC分类号： H01L21/2885 ,  C25D5/18 ,  C25D7/123 ,  C25D17/001 ,  C25D17/007 ,  H01L21/76877

摘要： A method of electroplating conductive material on semiconductor wafers controls undesirable surface defects by reducing the electroplating current as the wafer is being initially immersed in a plating bath. Further defect reduction and improved bottom up plating of vias is achieved by applying a static charge on the wafer before it is immersed in the bath, in order to enhance bath accelerators used to control the plating rate. The static charge is applied to the wafer using a supplemental electrode disposed outside the plating bath.

摘要翻译： 在半导体晶片上电镀导电材料的方法通过在晶片最初浸入电镀槽中时减少电镀电流来控制不期望的表面缺陷。 通过在晶片浸入槽中之前对晶片施加静电电荷，以便增强用于控制电镀速率的浴加速器，可实现进一步的缺陷减少和改进的底部电镀通孔。 使用布置在电镀液外部的辅助电极将静电荷施加到晶片。

公开(公告)号：US20110068466A1

公开(公告)日：2011-03-24

申请号：US12832019

申请日：2010-07-07

申请人： Ming-Fa Chen ,  Wen-Chih Chiou ,  Shau-Lin Shue

发明人： Ming-Fa Chen ,  Wen-Chih Chiou ,  Shau-Lin Shue

IPC分类号： H01L23/498

CPC分类号： H01L24/81 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05025 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2224/811 ,  H01L2224/8136 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2224/05552 ,  H01L2924/00

摘要： An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.

摘要翻译： 集成电路结构包括具有前表面和后表面的半导体衬底; 穿过半导体衬底的导电通孔; 以及在半导体衬底的后表面上的金属特征。 金属特征包括覆盖并接触导电通孔的金属焊盘以及导电通孔上方的金属线。 金属线包括双镶嵌结构。 集成电路结构还包括覆盖金属线的凸块。

公开(公告)号：US07704368B2

公开(公告)日：2010-04-27

申请号：US11043601

申请日：2005-01-25

申请人： Chung-Liang Chang ,  Shau-Lin Shue

发明人： Chung-Liang Chang ,  Shau-Lin Shue

IPC分类号： C25D7/12

CPC分类号： H01L21/2885 ,  C25D5/18 ,  C25D7/123 ,  C25D17/001 ,  C25D17/007 ,  H01L21/76877

摘要： A method of electroplating conductive material on semiconductor wafers controls undesirable surface defects by reducing the electroplating current as the wafer is being initially immersed in a plating bath. Further defect reduction and improved bottom up plating of vias is achieved by applying a static charge on the wafer before it is immersed in the bath, in order to enhance bath accelerators used to control the plating rate. The static charge is applied to the wafer using a supplemental electrode disposed outside the plating bath.

摘要翻译： 在半导体晶片上电镀导电材料的方法通过在晶片最初浸入电镀槽中时减少电镀电流来控制不期望的表面缺陷。 通过在晶片浸入槽中之前对晶片施加静电电荷，以便增强用于控制电镀速率的浴加速器，可实现进一步的缺陷减少和改进的底部电镀通孔。 使用布置在电镀液外部的辅助电极将静电荷施加到晶片。

公开(公告)号：US07625801B2

公开(公告)日：2009-12-01

申请号：US11523678

申请日：2006-09-19

申请人： Chii-Ming Wu ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

发明人： Chii-Ming Wu ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC分类号： H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/2658 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/78654

摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a gate stack on the semiconductor substrate, forming a silicon-containing compound stressor adjacent the gate stack, implanting non-siliciding ions into the silicon-containing compound stressor to amorphize an upper portion of the silicon-containing compound stressor, forming a metal layer on the silicon-containing compound stressor while the upper portion of the SiGe stressor is amorphous, and annealing to react the metal layer with the silicon-containing compound stressor to form a silicide region. The silicon-containing compound stressor includes SiGe or SiC.

摘要翻译： 一种用于形成半导体结构的方法包括：提供半导体衬底，在半导体衬底上形成栅极叠层，在栅堆叠附近形成含硅化合物应力源，将非硅化离子注入到含硅化合物应力器中以使上层 含硅化合物应激源的部分，在含硅化合物应激物上形成金属层，同时SiGe应力源的上部是无定形的，退火使金属层与含硅化合物应激反应物形成硅化物区域 。 含硅化合物应激源包括SiGe或SiC。

公开(公告)号：US07514348B2

公开(公告)日：2009-04-07

申请号：US11860639

申请日：2007-09-25

申请人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

发明人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

IPC分类号： H01L21/302

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76874 ,  H01L2221/1089

摘要： A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the hole or trench by means of PVD. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. A number of process variations are described including double etch/deposit steps, varying pressure and voltage in the same chamber to allow sputter etching and deposition to take place without breaking vacuum, and reduction of contact resistance between wiring levels by reducing via depth.

摘要翻译： 描述了在集成电路的表面处填充孔或沟槽而不在填充材料内捕获空隙的一般方法。 具体应用是用铜填充沟槽以形成镶嵌线。 首先，通过PVD将种子层沉积在孔或沟槽中。 然后进行溅射蚀刻步骤，其移除沟槽或孔口处的该种子层的任何突出端。 描述了许多工艺变化，包括双重蚀刻/沉积步骤，在相同的室中改变压力和电压，以允许在不破坏真空的情况下进行溅射蚀刻和沉积，并且通过减小通孔深度来降低布线水平之间的接触电阻。

公开(公告)号：US07443029B2

公开(公告)日：2008-10-28

申请号：US11201845

申请日：2005-08-11

申请人： Jing Cheng Lin ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

发明人： Jing Cheng Lin ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76843 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76873 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A new method and structure is provided for the creation of a copper dual damascene interconnect. A dual damascene structure is created in the layer of dielectric, optionally a metal barrier layer is deposited over exposed surfaces of the dual damascene structure. A copper seed layer is deposited, the dual damascene structure is filled with copper. An anneal is applied to the created copper interconnect after which excess copper is removed from the dielectric. Of critical importance to the invention, a thin layer of oxide is then deposited as a cap layer over the copper dual damascene interconnect, an etch stop layer is then deposited over the thin layer of oxide for continued upper-level metallization.

摘要翻译： 提供了一种新的方法和结构，用于创建铜双镶嵌互连。 在电介质层中产生双镶嵌结构，任选地，金属阻挡层沉积在双镶嵌结构的暴露表面上。 沉积铜籽晶层，双镶嵌结构填充铜。 对所制造的铜互连进行退火，之后从电介质去除多余的铜。 对本发明至关重要的是，然后在铜双镶嵌互连件上沉积薄层的氧化物作为覆盖层，然后将蚀刻停止层沉积在氧化物薄层上用于持续的上层金属化。

公开(公告)号：US07423347B2

公开(公告)日：2008-09-09

申请号：US11334849

申请日：2006-01-19

申请人： Chung-Hsien Chen ,  Chun-Chieh Lin ,  Minghsing Tsai ,  Shau-Lin Shue

发明人： Chung-Hsien Chen ,  Chun-Chieh Lin ,  Minghsing Tsai ,  Shau-Lin Shue

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/53238 ,  H01L21/2885 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor interconnect structure having reduced hillock formation and a method for forming the same are provided. The semiconductor interconnect structure includes a conductor formed in a dielectric layer. The conductor includes at least three sub-layers, wherein the ratio of the impurity concentrations in neighboring sub-layers is preferably greater than about two.

摘要翻译： 提供了具有减小的小丘形成的半导体互连结构及其形成方法。 半导体互连结构包括形成在电介质层中的导体。 导体包括至少三个子层，其中相邻子层中杂质浓度的比优选大于约2。