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    Semiconductor wafer carrier
    5.
    发明授权
    Semiconductor wafer carrier 有权
    半导体晶圆载体

    公开(公告)号：US08820728B2

    公开(公告)日：2014-09-02

    申请号：US12617851

    申请日：2009-11-13

    申请人： Jao Sheng Huang ,  Ming-Fa Chen

    发明人： Jao Sheng Huang ,  Ming-Fa Chen

    IPC分类号： B23Q3/00

    CPC分类号： H01L21/67346 ,  H01L21/67132

    摘要： A system and a method for protecting semiconductor wafers is disclosed. A preferred embodiment comprises a carrier with a central region and an exterior region. The exterior region preferably has a thickness that is greater than the central region, to form a cavity in the carrier. An adhesive is preferably placed into the cavity, and a semiconductor wafer is placed onto the adhesive. The edges of the semiconductor wafer are protected by the raised exterior region as well as the displaced adhesive that at least partially fills the area between the semiconductor wafer and the exterior region of the carrier.

    摘要翻译： 公开了一种用于保护半导体晶片的系统和方法。 优选实施例包括具有中心区域和外部区域的载体。 外部区域优选具有大于中心区域的厚度，以在载体中形成空腔。 优选将粘合剂放置在空腔中，并将半导体晶片放置在粘合剂上。 半导体晶片的边缘被凸起的外部区域以及至少部分地填充半导体晶片和载体的外部区域之间的区域的移位的粘合剂保护。

    Integrated circuits including metal-insulator-metal capacitors and methods of forming the same
    6.
    发明授权
    Integrated circuits including metal-insulator-metal capacitors and methods of forming the same 有权
    包括金属 - 绝缘体 - 金属电容器的集成电路及其形成方法

    公开(公告)号：US08546235B2

    公开(公告)日：2013-10-01

    申请号：US13101788

    申请日：2011-05-05

    申请人： Sung-Hui Huang ,  Yuan-Hung Liu ,  Ming-Fa Chen

    发明人： Sung-Hui Huang ,  Yuan-Hung Liu ,  Ming-Fa Chen

    IPC分类号： H01L21/20

    CPC分类号： H01L28/40

    摘要： An integrated circuit includes a substrate and a first metal-insulator-metal (MIM) capacitor disposed over the substrate. The MIM capacitor includes a first metallic capacitor plate disposed over the substrate. At least one first insulator layer is disposed over the first metallic capacitor plate. A second metallic capacitor plate is disposed over the at least one first insulator layer. At least one first dielectric layer is disposed over the substrate. At least a portion of the at least one first dielectric layer is disposed between the first metallic capacitor plate and the at least one first insulator layer.

    摘要翻译： 集成电路包括衬底和设置在衬底上的第一金属 - 绝缘体 - 金属（MIM）电容器。 MIM电容器包括设置在基板上的第一金属电容器板。 至少一个第一绝缘体层设置在第一金属电容器板上。 第二金属电容器板设置在至少一个第一绝缘体层上。 至少一个第一电介质层设置在衬底上。 所述至少一个第一介电层的至少一部分设置在所述第一金属电容器板和所述至少一个第一绝缘体层之间。

    Integrated circuits and methods of forming the same
    7.
    发明授权
    Integrated circuits and methods of forming the same 有权
    集成电路及其形成方法

    公开(公告)号：US08362591B2

    公开(公告)日：2013-01-29

    申请号：US12795734

    申请日：2010-06-08

    申请人： Hsiao-Tsung Yen ,  Hsien-Pin Hu ,  Jhe-Ching Lu ,  Chin-Wei Kuo ,  Ming-Fa Chen ,  Sally Liu

    发明人： Hsiao-Tsung Yen ,  Hsien-Pin Hu ,  Jhe-Ching Lu ,  Chin-Wei Kuo ,  Ming-Fa Chen ,  Sally Liu

    IPC分类号： H01L29/93

    CPC分类号： H01L27/016 ,  H01L29/93

    摘要： A three-dimensional integrated circuit includes a semiconductor substrate where the substrate has an opening extending through a first surface and a second surface of the substrate and where the first surface and the second surface are opposite surfaces of the substrate. A conductive material substantially fills the opening of the substrate to form a conductive through-substrate-via (TSV). An active circuit is disposed on the first surface of the substrate, an inductor is disposed on the second surface of the substrate and the TSV is electrically coupled to the active circuit and the inductor. The three-dimensional integrated circuit may include a varactor formed from a dielectric layer formed in the opening of the substrate such that the conductive material is disposed adjacent the dielectric layer and an impurity implanted region disposed surrounding the TSV such that the dielectric layer is formed between the impurity implanted region and the TSV.

    摘要翻译： 三维集成电路包括半导体衬底，其中衬底具有延伸穿过衬底的第一表面和第二表面的开口，并且其中第一表面和第二表面是与衬底相对的表面。 导电材料基本上填充衬底的开口以形成导电的通过衬底通孔（TSV）。 有源电路设置在衬底的第一表面上，电感器设置在衬底的第二表面上，并且TSV电耦合到有源电路和电感器。 三维集成电路可以包括由形成在基板的开口中的电介质层形成的变容二极管，使得导电材料邻近介电层设置，以及设置在TSV周围的杂质注入区域，使得介电层形成在 杂质注入区和TSV。

    Photomask arrangement protecting reticle patterns from electrostatic discharge damage (ESD)
    10.
    发明授权
    Photomask arrangement protecting reticle patterns from electrostatic discharge damage (ESD) 失效
    保护掩模版图案免受静电放电损坏（ESD）的光掩模布置

    公开(公告)号：US5989754A

    公开(公告)日：1999-11-23

    申请号：US923980

    申请日：1997-09-05

    申请人： Shih-Shiung Chen ,  Ming-Fa Chen ,  Ho-Ku Lan ,  Ying-Chen Chao

    发明人： Shih-Shiung Chen ,  Ming-Fa Chen ,  Ho-Ku Lan ,  Ying-Chen Chao

    IPC分类号： G03F1/00 ,  G03F1/40 ,  G03F9/00

    CPC分类号： G03F1/40

    摘要： A photomask arrangement is disclosed to prevent the reticle patterns of a photomask from peeling caused by electrostatic discharge damage. The photomask includes: a substrate; a plurality of metal shielding layers formed on the surface of the substrate to provide the reticle patterns, wherein each two of the metal shielding layers are spaced apart by a clear scribe line; and a plurality of metal lines formed on the clear scribe line to connect the adjacent metal shielding layers, thereby increasing the effective surface area of the reticle patterns.

    摘要翻译： 公开了一种光掩模布置，以防止光掩模的掩模版图案由静电放电损坏引起的剥离。 光掩模包括：基底; 形成在所述基板表面上的多个金属屏蔽层，以提供所述标线图案，其中每个所述金属屏蔽层通过清晰的划线间隔开; 以及形成在清晰划线上的多条金属线，以连接相邻的金属屏蔽层，从而增加标线图案的有效表面积。