公开(公告)号：US08791549B2

公开(公告)日：2014-07-29

申请号：US12832019

申请日：2010-07-07

申请人： Ming-Fa Chen ,  Wen-Chih Chiou ,  Shau-Lin Shue

发明人： Ming-Fa Chen ,  Wen-Chih Chiou ,  Shau-Lin Shue

IPC分类号： H01L29/40 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L24/81 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05025 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2224/811 ,  H01L2224/8136 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2224/05552 ,  H01L2924/00

摘要： An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.

摘要翻译： 集成电路结构包括具有前表面和后表面的半导体衬底; 穿过半导体衬底的导电通孔; 以及在半导体衬底的后表面上的金属特征。 金属特征包括覆盖并接触导电通孔的金属焊盘以及导电通孔上方的金属线。 金属线包括双镶嵌结构。 集成电路结构还包括覆盖金属线的凸块。

公开(公告)号：US20110068466A1

公开(公告)日：2011-03-24

申请号：US12832019

申请日：2010-07-07

申请人： Ming-Fa Chen ,  Wen-Chih Chiou ,  Shau-Lin Shue

发明人： Ming-Fa Chen ,  Wen-Chih Chiou ,  Shau-Lin Shue

IPC分类号： H01L23/498

CPC分类号： H01L24/81 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05025 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2224/811 ,  H01L2224/8136 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2224/05552 ,  H01L2924/00

摘要： An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.

摘要翻译： 集成电路结构包括具有前表面和后表面的半导体衬底; 穿过半导体衬底的导电通孔; 以及在半导体衬底的后表面上的金属特征。 金属特征包括覆盖并接触导电通孔的金属焊盘以及导电通孔上方的金属线。 金属线包括双镶嵌结构。 集成电路结构还包括覆盖金属线的凸块。

公开(公告)号：US08252665B2

公开(公告)日：2012-08-28

申请号：US12769725

申请日：2010-04-29

申请人： Wen-Chih Chiou ,  Weng-Jin Wu ,  Shau-Lin Shue

发明人： Wen-Chih Chiou ,  Weng-Jin Wu ,  Shau-Lin Shue

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L23/49811 ,  H01L21/561 ,  H01L21/6836 ,  H01L21/76898 ,  H01L24/81 ,  H01L24/94 ,  H01L25/50 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/81001 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00

摘要： A wafer is attached to a carrier by using an adhesive layer, and a portion of the adhesive layer is exposed adjacent to an edge of the wafer. After thinning the wafer, a protection layer is provided to cover the exposed portion of the adhesive layer. A plurality of dies is bonded onto the thinned wafer, and then the thinned wafer and the dies are encapsulated with a molding compound.

摘要翻译： 通过使用粘合剂层将晶片附接到载体，并且粘合剂层的一部分暴露于晶片的边缘附近。 在使晶片变薄之后，提供保护层以覆盖粘合剂层的暴露部分。 将多个模具结合到薄的晶片上，然后用模塑料封装薄化的晶片和模具。

公开(公告)号：US06736701B1

公开(公告)日：2004-05-18

申请号：US09989838

申请日：2001-11-20

申请人： Shau-Lin Shue ,  Ying-Ho Chen ,  Wen-Chih Chiou ,  Tsu Shih ,  Syun-Ming Jang

发明人： Shau-Lin Shue ,  Ying-Ho Chen ,  Wen-Chih Chiou ,  Tsu Shih ,  Syun-Ming Jang

IPC分类号： B24B100

CPC分类号： B24B37/042 ,  B24B21/04

摘要： A new method is provided for the post-deposition treatment of copper lines. A damascene copper line pattern whereby a TaN barrier layer and a seed layer have been provided is polished. Under the first embodiment of the invention, the deposited copper is polished (Cu CMP), the surface of the wafer is rinsed using a first High Flow DI rinse that contains a TBA inhibitor. The TaN CMP is performed immediately following the first High Flow DI rinse. A second High Flow DI rinse is applied using DI water that contains TBA inhibitor. The required following rinse step is executed immediately after the second High Flow DI rinse has been completed. Under the second embodiment of the invention, the process of CMP has been divided in two distinct steps where the first step is aimed at corrosion elimination and the second step is aimed at elimination of mechanical damage to the polished copper. The processing conditions for the second processing step have been extended and optimized, thereby using a second belt of a CMP apparatus.

摘要翻译： 提供了一种新的铜线后处理方法。 抛光已经提供TaN阻挡层和种子层的镶嵌铜线图案。 在本发明的第一实施例中，抛光沉积的铜（Cu CMP），使用含有TBA抑制剂的第一高流量DI冲洗冲洗晶片的表面。 在第一次高流量DI冲洗之后立即执行TaN CMP。 使用含有TBA抑制剂的去离子水进行第二次高流量DI冲洗。 第二次高流量DI冲洗完成后立即执行所需的冲洗步骤。 在本发明的第二个实施方案中，CMP的方法分为两个不同的步骤，其中第一步骤旨在消除腐蚀，第二步骤旨在消除抛光铜的机械损伤。 第二处理步骤的处理条件已被扩展和优化，从而使用CMP设备的第二带。

公开(公告)号：US08647925B2

公开(公告)日：2014-02-11

申请号：US12792975

申请日：2010-06-03

申请人： Wen-Chih Chiou ,  Shau-Lin Shue ,  Weng-Jin Wu ,  Ju-Pin Hung

发明人： Wen-Chih Chiou ,  Shau-Lin Shue ,  Weng-Jin Wu ,  Ju-Pin Hung

IPC分类号： H01L21/00

CPC分类号： H01L21/76898 ,  H01L21/6836 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/14181 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/00

摘要： A wafer is provided with a through via extending a portion of a substrate, an interconnect structure electrically connecting the through via, and a polyimide layer formed on the interconnect structure. Surface modification of the polyimide layer is the formation of a thin dielectric film on the polyimide layer by coating, plasma treatment, chemical treatment, or deposition methods. The thin dielectric film is adhered strongly to the polyimide layer, which can reduce the adhesion between the wafer surface and an adhesive layer formed in subsequent carrier attaching process.

摘要翻译： 晶片设置有延伸基板的一部分的通孔，连接通孔的互连结构和形成在互连结构上的聚酰亚胺层。 聚酰亚胺层的表面改性是通过涂覆，等离子体处理，化学处理或沉积方法在聚酰亚胺层上形成薄的电介质膜。 薄的电介质膜牢固地粘附到聚酰亚胺层，这可以降低晶片表面和随后的载体附接过程中形成的粘合剂层之间的粘合性。

公开(公告)号：US08441136B2

公开(公告)日：2013-05-14

申请号：US13560200

申请日：2012-07-27

申请人： Wen-Chih Chiou ,  Weng-Jin Wu ,  Shau-Lin Shue

发明人： Wen-Chih Chiou ,  Weng-Jin Wu ,  Shau-Lin Shue

IPC分类号： H01L23/29

CPC分类号： H01L23/49811 ,  H01L21/561 ,  H01L21/6836 ,  H01L21/76898 ,  H01L24/81 ,  H01L24/94 ,  H01L25/50 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/81001 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00

摘要： This description relates to a semiconductor device including a wafer having a first surface and a second surface opposite to the first surface and a carrier attached to the first surface of the wafer by an adhesive layer, a portion of the adhesive layer adjacent to an edge of the wafer is exposed. The semiconductor device further includes a protection layer to cover the exposed portion of the adhesive layer. The semiconductor device further includes a plurality of dies attached to the second surface and a molding compound encapsulating the plurality of dies.

摘要翻译： 本说明书涉及包括具有第一表面和与第一表面相对的第二表面的晶片的半导体器件和通过粘合剂层附着到晶片的第一表面的载体，粘合剂层的与边缘的边缘相邻的部分 晶片暴露。 半导体器件还包括保护层以覆盖粘合剂层的暴露部分。 半导体器件还包括附接到第二表面的多个管芯和封装多个管芯的模制化合物。

公开(公告)号：US07883991B1

公开(公告)日：2011-02-08

申请号：US12707752

申请日：2010-02-18

申请人： Wen-Jin Wu ,  Wen-Chih Chiou ,  Shau-Lin Shue

发明人： Wen-Jin Wu ,  Wen-Chih Chiou ,  Shau-Lin Shue

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2224/05552

摘要： A method of bonding and detaching a temporary carrier used for handling a wafer during the fabrication of semiconductor devices includes bonding a wafer onto a carrier through a first adhesive layer and a second adhesive layer, in which the edge zone of the wafer and the carrier is covered by the first adhesive layer while the edge zone is not covered by the second adhesive layer. A wafer edge clean process is then performed to remove the first adhesive layer adjacent the edge of the wafer and expose the edge zone of the carrier, followed by removing the second adhesive layer from the carrier. After detaching the carrier from the wafer, the first adhesive layer remaining on the wafer is removed.

摘要翻译： 在半导体器件的制造期间，接合和分离用于处理晶片的临时载体的方法包括通过第一粘合剂层和第二粘合剂层将晶片接合到载体上，其中晶片和载体的边缘区域 被第一粘合剂层覆盖，而边缘区域不被第二粘合剂层覆盖。 然后进行晶片边缘清洁工艺以除去邻近晶片边缘的第一粘合剂层，并暴露载体的边缘区域，然后从载体上除去第二粘合剂层。 在从晶片上分离载体之后，去除残留在晶片上的第一粘合剂层。

公开(公告)号：US09324756B2

公开(公告)日：2016-04-26

申请号：US13558063

申请日：2012-07-25

申请人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Jing-Cheng Lin

发明人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Jing-Cheng Lin

IPC分类号： H01L31/0232 ,  H01L27/146 ,  H01L31/02 ,  H01L21/768 ,  H01L23/48 ,  H01L21/683 ,  H01L23/00

CPC分类号： H01L27/14689 ,  H01L21/6835 ,  H01L21/76834 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/13 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14687 ,  H01L31/02002 ,  H01L31/02327 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/023 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014

摘要： A device includes a semiconductor substrate, an image sensor at a front surface of the semiconductor substrate, and a plurality of dielectric layers over the image sensor. A color filter and a micro lens are disposed over the plurality of dielectric layers and aligned to the image sensor. A through via penetrates through the semiconductor substrate. A Redistribution Line (RDL) is disposed over the plurality of dielectric layers, wherein the RDL is electrically coupled to the through via. A polymer layer covers the RDL.

摘要翻译： 一种器件包括半导体衬底，在半导体衬底的前表面处的图像传感器和图像传感器上的多个电介质层。 滤色器和微透镜设置在多个介电层上并与图像传感器对准。 穿通通孔穿过半导体衬底。 再分配线（RDL）设置在多个介电层上，其中RDL电连接到通孔。 聚合物层覆盖RDL。

公开(公告)号：US08953336B2

公开(公告)日：2015-02-10

申请号：US13412958

申请日：2012-03-06

申请人： Chin-Fu Kao ,  Wen-Chih Chiou ,  Jing-Cheng Lin ,  Cheng-Lin Huang ,  Po-Hao Tsai

发明人： Chin-Fu Kao ,  Wen-Chih Chiou ,  Jing-Cheng Lin ,  Cheng-Lin Huang ,  Po-Hao Tsai

IPC分类号： H05K7/10

CPC分类号： H01L24/14 ,  H01L22/32 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/14515 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/014

摘要： A surface metal wiring structure for a substrate includes one or more functional μbumps formed of a first metal and an electrical test pad formed of a second metal for receiving an electrical test probe and electrically connected to the one or more functional μbumps. The surface metal wiring structure also includes a plurality of sacrificial μbumps formed of the first metal that are electrically connected to the electrical test pads, where the sacrificial μbumps are positioned closer to the electrical test pad than the one or more functional μbumps.

摘要翻译： 用于基板的表面金属布线结构包括由第一金属形成的一个或多个功能性μ凸块和由用于接收电测试探针并电连接到所述一个或多个功能性μ凸起的第二金属形成的电测试垫。 表面金属布线结构还包括由第一金属形成的多个牺牲μ凸块，其电连接到电测试焊盘，其中牺牲μ凸块位于比一个或多个功能性μ凸块更靠近电测试垫的位置。

公开(公告)号：US08900994B2

公开(公告)日：2014-12-02

申请号：US13157137

申请日：2011-06-09

申请人： Chen-Hua Yu ,  Shin-Puu Jeng ,  Wen-Chih Chiou ,  Fang Wen Tsai ,  Chen-Yu Tsai

发明人： Chen-Hua Yu ,  Shin-Puu Jeng ,  Wen-Chih Chiou ,  Fang Wen Tsai ,  Chen-Yu Tsai

IPC分类号： H01L21/44 ,  H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/683

CPC分类号： H01L25/0657 ,  H01L21/0217 ,  H01L21/6835 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76871 ,  H01L21/76895 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05018 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05559 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/1411 ,  H01L2224/14181 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/01029 ,  H01L2224/05552

摘要： A system and method for manufacturing a through silicon via is disclosed. An embodiment comprises forming a through silicon via with a liner protruding from a substrate. A passivation layer is formed over the substrate and the through silicon via, and the passivation layer and liner are recessed from the sidewalls of the through silicon via. Conductive material may then be formed in contact with both the sidewalls and a top surface of the through silicon via.

摘要翻译： 公开了一种制造硅通孔的系统和方法。 一个实施例包括用从衬底突出的衬垫形成通孔硅通孔。 钝化层形成在衬底和穿通硅通孔之上，钝化层和衬垫从通硅通孔的侧壁凹陷。 然后可以将导电材料形成为与通孔硅通孔的两个侧壁和顶表面接触。