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95 条记录 (耗时 0.031 秒)

    Multichip module
    67.
    发明授权
    Multichip module 有权
    多芯片模块

    公开(公告)号：US06462421B1

    公开(公告)日：2002-10-08

    申请号：US09546627

    申请日：2000-04-10

    申请人： Kao-Yu Hsu ,  Su Tao

    发明人： Kao-Yu Hsu ,  Su Tao

    IPC分类号： H01L2940

    CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

    摘要： A multichip module mainly comprises a first chip disposed on the upper surface of a substrate by wire bonding and a second chip disposed on the lower surface of the substrate by flip-chip bonding wherein the first chip and the second chip are of the same type. The upper surface of the substrate is provided with a plurality of wire bondable pads for electrical connecting to the first chip. The lower surface of the substrate is provided with a plurality of flip-chip pads for electrical connecting to the second chip. According to the present invention, the first and second chips are both oriented face up (with their bonding pads up with respect to the substrate) for bonding to the substrate. Thus, address assignment of the bonding pads on the two semiconductor chips conforms to each other. Consequently, circuit layout on the upper and lower surfaces of the substrate can use substantially the same design wherein common conductive traces on the upper and lower surfaces of the substrate are electrically connected by plated through holes.

    摘要翻译： 多芯片模块主要包括通过引线键合设置在基板的上表面上的第一芯片和通过倒装芯片接合设置在基板的下表面上的第二芯片，其中第一芯片和第二芯片是相同类型的。 衬底的上表面设置有用于电连接到第一芯片的多个可焊接焊盘。 衬底的下表面设置有用于电连接到第二芯片的多个倒装芯片焊盘。 根据本发明，第一和第二芯片既面向上（其相对于基板的接合焊盘向上），用于粘合到基板。 因此，两个半导体芯片上的接合焊盘的地址分配彼此一致。 因此，在基板的上表面和下表面上的电路布局可以使用基本上相同的设计，其中基板的上表面和下表面上的公共导电迹线通过电镀通孔电连接。

    Press plate of wire bond checking system
    68.
    发明授权
    Press plate of wire bond checking system 有权
    线焊检查系统压板

    公开(公告)号：US06392424B1

    公开(公告)日：2002-05-21

    申请号：US09373187

    申请日：1999-08-12

    申请人： Chin-Chen Wang ,  Yao-Hsin Feng ,  Su Tao

    发明人： Chin-Chen Wang ,  Yao-Hsin Feng ,  Su Tao

    IPC分类号： G01R3102

    CPC分类号： G01R1/0408

    摘要： A press plate mainly includes a plate and a probe. The plate has an opening which corresponds to a chip of the substrate and inner finger thereof, and the probe is elastically attached to the edge of the opening for wire bond checking. After the wire bonding process, the wire connecting the chip and the inner finger of the substrate and the probe of the wire bond checking system form a loop. Then a current is sent to the substrate from the wire bond checking system to check for the occurrence of wire occurring lift bond or missing wire.

    摘要翻译： 压板主要包括板和探针。 该板具有对应于基板和其内指的芯片的开口，并且探针弹性地附接到开口的边缘以进行引线键合检查。 在引线接合工艺之后，连接芯片和基板的内指以及引线键合检查系统的探针的导线形成环路。 然后从线焊检查系统将电流发送到基板，以检查发生电线接合或缺失电线的发生。

    Strip of semiconductor package
    69.
    发明授权
    Strip of semiconductor package 有权
    半导体封装条

    公开(公告)号：US06369439B1

    公开(公告)日：2002-04-09

    申请号：US09366637

    申请日：1999-08-04

    申请人： Su Tao ,  Kuo-Pin Yang ,  Tai-Chun Huang

    发明人： Su Tao ,  Kuo-Pin Yang ,  Tai-Chun Huang

    IPC分类号： H01L23465

    CPC分类号： H01L23/13 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2924/3511 ,  H01L2924/00014

    摘要： A strip mainly includes a plurality of guide holes, a plurality of position holes, a plurality of separation holes, a plurality of second slots and a plurality of substrate areas. Guide holes are arranged on two sides of the strip for carrying during processing, and position holes are arranged at four corners of the strip for positioning on the machine during processing. Separation holes and slots are to be contiguous to the substrate areas and separate the substrate areas from one another so that the discontinuous warpage of the substrate area affects the peripheral substrate areas. Therefore, it can reduce the chance of breaking chip in the substrate area. The two ends of the substrate are adjacent to the slots to reduce the stress of other substrates in the longitudinal direction actuating the chip during heat treatment in processing. The strip further includes a metal layer surrounding the substrate areas to increase the stiffness of the entirety of the strip.

    摘要翻译： 一条带主要包括多个导向孔，多个位置孔，多个分隔孔，多个第二槽和多个基板区域。 引导孔布置在条的两侧，用于在加工过程中传送，并且定位孔布置在条的四个角处，用于在加工期间定位在机器上。 分离孔和槽将与衬底区域相邻并且将衬底区域彼此分开，使得衬底区域的不连续翘曲影响外围衬底区域。 因此，可以减少在基板区域中芯片断裂的机会。 衬底的两端与槽相邻，以减少处理过程中热处理期间致动芯片的纵向方向上的其它衬底的应力。 条带还包括围绕衬底区域的金属层，以增加整个条带的刚度。

    Method for manufacturing leadless semiconductor chip package
    70.
    发明授权
    Method for manufacturing leadless semiconductor chip package 有权
    无铅半导体芯片封装的制造方法

    公开(公告)号：US06312976B1

    公开(公告)日：2001-11-06

    申请号：US09444366

    申请日：1999-11-22

    申请人： Chun Hung Lin ,  Chun-Chi Lee ,  Su Tao

    发明人： Chun Hung Lin ,  Chun-Chi Lee ,  Su Tao

    IPC分类号： H01L2144

    CPC分类号： H01L21/565 ,  H01L23/49548 ,  H01L23/49833 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

    摘要： A method of manufacturing a leadless semiconductor chip package comprises the steps of: attaching a semiconductor die onto a die pad of a lead frame, wherein the lead frame comprises a plurality of leads arranged about the periphery of the die pad and each lead has a notch formed at the to-be-punched position thereof; wire bonding the inner ends of the leads to bonding pads on the semiconductor die; sucking a film against a lower part of a molding die; closing and clamping the molding die in a manner that the semiconductor die is positioned in a cavity of the molding die and the lead frame is disposed against the film; transferring a hardenable molding compound into the cavity; hardening the molding compound; opening the molding die to take out the molded product; and punching the molded product along the notches of the leads thereby making the singulation process more convenient and correct. The lower surface of each lead of the lead frame according to the present invention is smaller than the upper surface thereof such that each lead has a tapered profile which cooperates with the film to provide better sealing effect thereby preventing the formation of flash.

    摘要翻译： 一种制造无引线半导体芯片封装的方法包括以下步骤：将半导体管芯附接到引线框架的管芯焊盘上，其中引线框架包括围绕管芯焊盘的周边布置的多个引线，并且每个引线具有缺口 形成在被打孔的位置; 将引线的内端引线接合到半导体管芯上的接合焊盘; 将薄膜吸附在成型模具的下部; 以半导体管芯位于成型模具的空腔中的方式封闭和夹紧成型模具，并且引线框架抵靠薄膜设置; 将可硬化的模塑料转移到所述空腔中; 硬化模塑料; 打开成型模具取出成型品; 沿着导线的切口冲压模制产品，从而使切割过程更方便正确。 根据本发明的引线框架的每个引线的下表面小于其上表面，使得每个引线具有与膜配合的锥形轮廓，以提供更好的密封效果，从而防止闪光的形成。