METHOD FOR PERFORMING A PHOTOLITHOGRAPHY PROCESS

    公开(公告)号:US20190080901A1

    公开(公告)日:2019-03-14

    申请号:US15906187

    申请日:2018-02-27

    Abstract: A method for performing a photolithography process is provided. The method includes forming a resist layer over a substrate and exposing a portion of the resist layer to form an exposed region and an unexposed region by performing an exposure process. The method includes performing a baking process on the resist layer, so that voids are formed in the exposed region of the resist layer. The method also includes removing the unexposed region of the resist layer to form a recess in the resist layer and filling a post treatment coating material in the recess and the void. The method further includes removing a portion of the post treatment coating material by performing a second develop process, and another portion of the post treatment coating material is left on surfaces of the exposed region of the resist layer to form a patterned resist layer.

    PHOTORESIST TOP COATING MATERIAL FOR ETCHING RATE CONTROL

    公开(公告)号:US20220334482A1

    公开(公告)日:2022-10-20

    申请号:US17231946

    申请日:2021-04-15

    Abstract: A patterning stack is provided. The patterning stack includes a bottom anti-reflective coating (BARC) layer over a substrate, a photoresist layer having a first etching resistance over the BARC layer, and a top coating layer having a second etching resistance greater than the first etching resistance over the photoresist layer. The top coating layer includes a polymer having a polymer backbone including at least one functional unit of high etching resistance and one or more acid labile groups attached to the polymer backbone or a silicon cage compound.

    RESIST DISPENSING SYSTEM AND METHOD OF USE

    公开(公告)号:US20220308452A1

    公开(公告)日:2022-09-29

    申请号:US17214660

    申请日:2021-03-26

    Abstract: In a method, a resist material is dispensed through a tube of a nozzle of a resist pump system on a wafer. The tube extends from a top to a bottom of the nozzle and has upper, lower, and middle segments. When not dispensing, the resist material is retracted from the lower and the middle segments, and maintained in the upper segment of the tube. When retracting, a first solvent is flown through a tip of the nozzle at the bottom of the nozzle to fill the lower segment of the tube with the first solvent and to produce a gap in the middle segment of the tube between the resist material and the first solvent. The middle segment includes resist material residues on an inner surface wall of the tube and vapor of the first solvent. The vapor of the first solvent prevents the resist material residues from drying.

    CAPPING LAYER FOR GATE ELECTRODES
    70.
    发明申请

    公开(公告)号:US20210384322A1

    公开(公告)日:2021-12-09

    申请号:US17408985

    申请日:2021-08-23

    Abstract: The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer having a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.

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