公开(公告)号：US20120256321A1

公开(公告)日：2012-10-11

申请号：US13084053

申请日：2011-04-11

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

IPC分类号： H01L23/48 ,  H01L21/50 ,  H01L21/78

CPC分类号： H01L21/561 ,  H01L23/3121 ,  H01L24/24 ,  H01L24/82 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/83005

摘要： A layered chip package includes a main body and wiring. The main body includes a main part including a plurality of stacked layer portions, and a plurality of terminals disposed on the top and bottom surfaces of the main part. The wiring includes a plurality of lines electrically connected to the plurality of terminals. The plurality of lines include a plurality of common lines and a plurality of layer-dependent lines. Each of the plurality of layer portions includes: a plurality of common electrodes electrically connected to the plurality of common lines; a plurality of non-contact electrodes that are electrically connected to the layer-dependent lines and are not in contact with the semiconductor chip in the layer portion; and a selective connection electrode selectively electrically connected to only the layer-dependent line that the layer portion uses among the plurality of layer-dependent lines. The layer-dependent lines are greater than the common lines in maximum width.

摘要翻译： 分层芯片封装包括主体和布线。 主体包括主要部分，其包括多个堆叠层部分，以及设置在主要部分的顶表面和底表面上的多个端子。 布线包括电连接到多个端子的多条线。 多条线包括多条公共线和多个依赖于层的线。 多个层部分中的每一个包括：电连接到多个公共线的多个公共电极; 多个非接触电极，其电连接到与层相关的线，并且不与层部分中的半导体芯片接触; 以及选择性连接电极，其仅选择性地电连接到所述层部分在多个层相关线中使用的与层相关的线。 层相关线大于最大宽度的公共线。

公开(公告)号：US20120025355A1

公开(公告)日：2012-02-02

申请号：US12848595

申请日：2010-08-02

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

IPC分类号： H01L23/544 ,  H01L21/00 ,  H01L23/552

CPC分类号： H01L23/552 ,  H01L21/6835 ,  H01L23/481 ,  H01L24/05 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05551 ,  H01L2224/05555 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/83005 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/96 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01029 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/3025 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/00

摘要： In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein. Further, an uppermost substrate and a lowermost substrate have electromagnetic shielding layer formed in regions other than the scribe-groove parts using a ferromagnetic body. Further, in the laminated semiconductor substrate, a through hole which penetrates the plurality of semiconductor substrates laminated in a laminated direction is formed in the scribe-groove part, and the laminated semiconductor substrate has a through electrode penetrating the plurality of semiconductor substrates through the through hole.

摘要翻译： 在层叠半导体衬底中层叠多个半导体衬底。 每个半导体衬底具有沿着划线形成的多个划线槽部分。 此外，每个半导体衬底具有彼此绝缘的多个器件区域，并且其中形成有半导体器件。 此外，最上面的基板和最下面的基板在使用铁磁体的划线槽部以外的区域中形成有电磁屏蔽层。 此外，在层叠半导体基板中，在划线槽部形成有贯穿层叠方向的多个半导体基板的贯通孔，并且层叠半导体基板具有穿过多个半导体基板的通孔， 孔。

公开(公告)号：US20110266692A1

公开(公告)日：2011-11-03

申请号：US12769361

申请日：2010-04-28

申请人： Yoshitaka SASAKI ,  Hiroyuki Ito ,  Atsushi Iijima ,  Tatsuya Harada

发明人： Yoshitaka SASAKI ,  Hiroyuki Ito ,  Atsushi Iijima ,  Tatsuya Harada

IPC分类号： H01L23/48 ,  H01L21/50 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L21/6835 ,  H01L22/22 ,  H01L23/3121 ,  H01L23/481 ,  H01L24/05 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/04105 ,  H01L2224/05551 ,  H01L2224/05554 ,  H01L2224/24146 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/82101 ,  H01L2224/83005 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/96 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01029 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/1453 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00

摘要： A layered chip package includes a main body and a plurality of through electrodes. The main body includes a plurality of layer portions stacked and a plurality of through holes that penetrate all the plurality of layer portions. The plurality of through electrodes are provided in the plurality of through holes of the main body and penetrate all the plurality of layer portions. Each of the plurality of layer portions includes a semiconductor chip. At least one of the plurality of layer portions includes wiring that electrically connects the semiconductor chip to the plurality of through electrodes. The wiring includes a plurality of conductors that make contact with a through electrode that is exposed in the wall faces of any one of the plurality of through holes and passes through the through hole.

摘要翻译： 分层芯片封装包括主体和多个贯通电极。 主体包括层叠的多个层部分和穿透所有多个层部分的多个通孔。 多个贯通电极设置在主体的多个通孔中，并穿透所有多个层部分。 多个层部分中的每一个包括半导体芯片。 多个层部分中的至少一个包括将半导体芯片电连接到多个贯通电极的布线。 布线包括多个导体，其与暴露在多个通孔中的任一个的壁面中的穿通电极接触并穿过通孔。

公开(公告)号：US20110189822A1

公开(公告)日：2011-08-04

申请号：US12700297

申请日：2010-02-04

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

IPC分类号： H01L21/78

CPC分类号： H01L21/78 ,  H01L2224/16

摘要： A layered chip package includes a main body and wiring. The main body includes a plurality of layer portions stacked. The wiring is disposed on at least one side surface of the main body. In the method of manufacturing the layered chip package, first, a plurality of substructures each of which includes an array of a plurality of preliminary layer portions are used to fabricate a layered substructure that includes a plurality of pre-separation main bodies arranged in rows. Next, the layered substructure is cut into a plurality of blocks each of which includes a row of a plurality of pre-separation main bodies, and the wiring is formed on the plurality of pre-separation main bodies included in each block simultaneously. The plurality of pre-separation main bodies are then separated from each other. Each of the plurality of blocks includes a row of three, four, or five pre-separation main bodies.

摘要翻译： 分层芯片封装包括主体和布线。 主体包括堆叠的多个层部分。 布线布置在主体的至少一个侧表面上。 在制造层状芯片封装的方法中，首先，使用多个子结构，每个子结构包括多个预备层部分的阵列，以制造包括排成行的多个预分离主体的分层子结构。 接下来，将分层子结构切割成多个块，每个块包括一行多个预分离主体，并且布线同时形成在包括在每个块中的多个预分离主体上。 然后将多个预分离主体彼此分离。 多个块中的每个块包括一行三个，四个或五个预分离主体。

公开(公告)号：US20120142146A1

公开(公告)日：2012-06-07

申请号：US12960921

申请日：2010-12-06

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

IPC分类号： H01L21/78

CPC分类号： H01L25/50 ,  H01L23/49805 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/24137 ,  H01L2225/06513 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/07802 ,  H01L2924/18162 ,  H01L2924/00

摘要： A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes a plurality of stacked layer portions. A method of manufacturing the layered chip package includes the step of fabricating a layered substructure and the step of cutting the layered substructure. The layered substructure includes: a plurality of arrayed pre-separation main bodies; a plurality of accommodation parts disposed between two adjacent pre-separation main bodies; and a plurality of preliminary wires accommodated in the accommodation parts. The accommodation parts are formed in a photosensitive resin layer by photolithography. In the step of cutting the layered substructure, the plurality of pre-separation main bodies are separated from each other, and the wires are formed by the preliminary wires.

摘要翻译： 分层芯片封装包括主体和布线，其包括布置在主体的侧表面上的多根导线。 主体包括多个堆叠层部分。 制造层状芯片封装的方法包括制造层状子结构的步骤和切割层状子结构的步骤。 分层子结构包括：多个排列的预分离主体; 设置在两个相邻的预分离主体之间的多个容纳部件; 以及容纳在容纳部中的多条初级线。 通过光刻在光敏树脂层中形成住宿部。 在切割层状子结构的步骤中，多个预分离主体彼此分离，并且通过初步线形成电线。

公开(公告)号：US20110189820A1

公开(公告)日：2011-08-04

申请号：US12700217

申请日：2010-02-04

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

IPC分类号： H01L21/50

CPC分类号： H01L24/96 ,  H01L21/6836 ,  H01L23/3178 ,  H01L23/544 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/24101 ,  H01L2224/24105 ,  H01L2224/24137 ,  H01L2224/24147 ,  H01L2224/25175 ,  H01L2224/2929 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/821 ,  H01L2224/8385 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2924/07802 ,  Y10S438/928 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： In a method of manufacturing a layered chip package, a layered substructure is fabricated and used to produce a plurality of layered chip packages. The layered substructure includes first to fourth substructures stacked, each of the substructures including an array of a plurality of preliminary layer portions. In the step of fabricating the layered substructure, initially fabricated are first to fourth pre-polishing substructures each having first and second surfaces. Next, the first and second pre-polishing substructures are bonded to each other with the first surfaces facing each other, and then the second surface of the second pre-polishing substructure is polished to form a first stack. Similarly, the third and fourth pre-polishing substructures are bonded to each other and the second surface of the third pre-polishing substructure is polished to form a second stack. Then, the first and second stacks are bonded to each other.

摘要翻译： 在制造层状芯片封装的方法中，制造层叠子结构并用于制造多个分层芯片封装。 分层子结构包括堆叠的第一至第四子结构，每个子结构包括多个预备层部分的阵列。 在制造层状子结构的步骤中，最初制造的是具有第一和第二表面的第一至第四预抛光子结构。 接下来，第一和第二预抛光子结构彼此接合，第一表面彼此面对，然后抛光第二预抛光子结构的第二表面以形成第一叠层。 类似地，第三和第四预抛光子结构彼此结合，并且抛光第三预抛光子结构的第二表面以形成第二堆叠。 然后，第一和第二堆叠彼此结合。

公开(公告)号：US20130075935A1

公开(公告)日：2013-03-28

申请号：US13240048

申请日：2011-09-22

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

IPC分类号： H01L23/52

CPC分类号： H01L24/96 ,  H01L21/6835 ,  H01L24/06 ,  H01L24/24 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03011 ,  H01L2224/0346 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/83005 ,  H01L2224/94 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/1064 ,  H01L2924/07802 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/0105

摘要： A composite layered chip package includes first and second subpackages that are stacked. Each subpackage includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface; first terminals disposed on the top surface of the main part; and second terminals disposed on the bottom surface of the main part. The first and second terminals are electrically connected to the wiring. The first and second subpackages are arranged in a specific relative positional relationship, different from a reference relative positional relationship, with each other.

摘要翻译： 复合分层芯片封装包括堆叠的第一和第二子封装。 每个子包包括主体和接线。 主体包括：具有顶表面和底表面的主要部分; 第一端子设置在主要部件的顶表面上; 以及设置在主要部分的底表面上的第二端子。 第一端子和第二端子电连接到布线。 第一子包和第二子包以不同于参考相对位置关系的特定相对位置关系彼此排列。

公开(公告)号：US20120313260A1

公开(公告)日：2012-12-13

申请号：US13156941

申请日：2011-06-09

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

IPC分类号： H01L23/48 ,  H01L21/30

CPC分类号： H01L23/5389 ,  H01L21/561 ,  H01L21/6835 ,  H01L22/22 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05008 ,  H01L2224/05013 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/1146 ,  H01L2224/13024 ,  H01L2224/13144 ,  H01L2224/16148 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/2512 ,  H01L2224/25171 ,  H01L2224/25175 ,  H01L2224/25177 ,  H01L2224/2746 ,  H01L2224/29024 ,  H01L2224/29144 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/75101 ,  H01L2224/8112 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/8313 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83986 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/1058 ,  H01L2924/07802 ,  H01L2924/0105 ,  H01L2224/82 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/0231 ,  H01L21/78 ,  H01L2224/81 ,  H01L2924/00

摘要： A layered chip package includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. Each layer portion includes a semiconductor chip having first and second surfaces, and a plurality of electrodes electrically connected to the wiring. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. A first layer portion located closest to the top surface of the main part and a second layer portion located closest to the bottom surface of the main part are arranged so that the second surfaces of their respective semiconductor chips face toward each other. The plurality of first terminals are formed by using the plurality of electrodes of the first layer portion. The plurality of second terminals are formed by using the plurality of electrodes of the second layer portion.

摘要翻译： 分层芯片封装包括主体和布线。 主体包括：具有顶表面和底表面并且包括彼此堆叠的三个或更多个层部分的主要部分; 多个第一端子，设置在所述主要部件的顶表面上; 以及设置在主要部分的底表面上的多个第二端子。 每个层部分包括具有第一和第二表面的半导体芯片和电连接到布线的多个电极。 多个电极设置在半导体芯片的第一表面的一侧。 位于最靠近主要部分的顶表面的第一层部分和最靠近主要部分的底表面的第二层部分被布置成使得它们各自的半导体芯片的第二表面朝向彼此。 多个第一端子通过使用第一层部分的多个电极形成。 多个第二端子通过使用第二层部分的多个电极形成。

公开(公告)号：US20120187575A1

公开(公告)日：2012-07-26

申请号：US13014418

申请日：2011-01-26

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

IPC分类号： H01L23/48 ,  H01L21/60

CPC分类号： H01L22/22 ,  H01L21/6835 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/92 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05011 ,  H01L2224/05013 ,  H01L2224/05569 ,  H01L2224/05644 ,  H01L2224/06155 ,  H01L2224/06165 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/9202 ,  H01L2224/96 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/07802 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/0105 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552

摘要： A layered chip package includes a main body and wiring. The main body includes a main part including a plurality of stacked layer portions, and a plurality of terminals disposed on the top and bottom surfaces of the main part. The wiring includes a plurality of lines electrically connected to the plurality of terminals. The plurality of lines include a plurality of common lines and a plurality of layer-dependent lines. Each of the plurality of layer portions includes a plurality of common electrodes electrically connected to the plurality of common lines, and a selective connection electrode selectively electrically connected to only the layer-dependent line that the layer portion uses among the plurality of layer-dependent lines. The selective connection electrode varies in shape depending on which of the layer-dependent lines it is electrically connected to.

摘要翻译： 分层芯片封装包括主体和布线。 主体包括主要部分，其包括多个堆叠层部分，以及设置在主要部分的顶表面和底表面上的多个端子。 布线包括电连接到多个端子的多条线。 多条线包括多条公共线和多个依赖于层的线。 多个层部分中的每一个包括电连接到多个公共线的多个公共电极，以及选择性连接电极，其选择性地电连接到多个层相关线之间的层部分使用的与层相关的线 。 选择性连接电极根据与电连接的层相关线路的形状而变化。

公开(公告)号：US20120126427A1

公开(公告)日：2012-05-24

申请号：US12949279

申请日：2010-11-18

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

IPC分类号： H01L23/52 ,  H01L21/768

CPC分类号： H01L25/0657 ,  H01L21/76232 ,  H01L24/24 ,  H01L24/82 ,  H01L24/95 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/03 ,  H01L2224/05554 ,  H01L2224/0556 ,  H01L2224/24101 ,  H01L2224/24145 ,  H01L2224/25175 ,  H01L2224/8385 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06551 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05552

摘要： A memory device has a laminated chip package and a controller chip. In the laminated chip package, a plurality of memory chips are laminated. An interposed chip is laminated between the laminated chip package and the controller chip. The memory chips have a plurality of first wiring electrodes. The interposed chip has a plurality of second wiring electrodes. The second wiring electrodes are formed with a common arrangement pattern common with an arrangement pattern of a plurality of wiring electrodes for controller which are formed in the controller chip. The controller chip is laid on the interposed chip.

摘要翻译： 存储器件具有层叠芯片封装和控制芯片。 在层叠芯片封装中，层叠多个存储芯片。 在层压芯片封装和控制器芯片之间层压插入的芯片。 存储芯片具有多个第一布线电极。 插入的芯片具有多个第二布线电极。 第二布线电极形成有与形成在控制器芯片中的多个用于控制器的布线电极的布置图案相同的共同布置图案。 控制器芯片放置在插入的芯片上。