公开(公告)号：US08704350B2

公开(公告)日：2014-04-22

申请号：US12458454

申请日：2009-07-13

申请人： Seung Wook Park ,  Young Do Kweon ,  Jin Gu Kim ,  Ju Pyo Hong ,  Hee Kon Lee ,  Hyung Jin Jeon ,  Jing Li Yuan ,  Jong Yun Lee

发明人： Seung Wook Park ,  Young Do Kweon ,  Jin Gu Kim ,  Ju Pyo Hong ,  Hee Kon Lee ,  Hyung Jin Jeon ,  Jing Li Yuan ,  Jong Yun Lee

IPC分类号： H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/2402 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83851 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2224/29075 ,  H01L2924/00014 ,  H01L2924/00

摘要： The present invention relates to a stacked wafer level package and a method of manufacturing the same. The stacked wafer level package in accordance with the present invention can improve a misalignment problem generated in a stacking process by performing a semiconductor chip mounting process, a rearrangement wiring layer forming process, the stacking process and so on after previously bonding internal connection means for interconnection between stacked electronic components to a conductive layer for forming a rearrangement wiring layer, thereby improving reliability and yield and reducing manufacturing cost.

摘要翻译： 本发明涉及层叠晶片级封装及其制造方法。 根据本发明的堆叠晶片级封装可以通过在预先接合用于互连的内部连接装置之后执行半导体芯片安装处理，重排布线层形成处理，堆叠处理等来改善堆叠处理中产生的未对准问题 在层叠的电子部件之间形成用于形成重排布线层的导电层，从而提高可靠性和产率，并降低制造成本。

公开(公告)号：US08143099B2

公开(公告)日：2012-03-27

申请号：US12453274

申请日：2009-05-05

申请人： Seung Wook Park ,  Jin Gu Kim ,  Jong Hwan Baek ,  Jong Yun Lee ,  Hyung Jin Jeon ,  Young Do Kweon

发明人： Seung Wook Park ,  Jin Gu Kim ,  Jong Hwan Baek ,  Jong Yun Lee ,  Hyung Jin Jeon ,  Young Do Kweon

IPC分类号： H01L21/00

CPC分类号： H01L21/4832 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/5389 ,  H01L2224/12105 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2224/0401

摘要： The present invention relates to a method of manufacturing a semiconductor package capable of simplifying a process and remarkably reducing a production cost by including the steps of: preparing a different bonded panel including at least one metal layer; forming a pad unit electrically connected to the metal layer; mounting a semiconductor chip over the different bonded panel to be electrically connected to the pad unit; sealing the semiconductor chip; forming a rearrangement wiring layer by etching the metal layer; and forming an external connection unit electrically connected to the rearrangement wiring layer.

摘要翻译： 本发明涉及一种制造半导体封装的方法，其能够简化工艺并显着降低生产成本，包括以下步骤：制备包括至少一个金属层的不同键合板; 形成电连接到所述金属层的焊盘单元; 将半导体芯片安装在所述不同的接合面板上以电连接到所述焊盘单元; 密封半导体芯片; 通过蚀刻金属层形成重排布线层; 以及形成与所述重排布线层电连接的外部连接单元。

公开(公告)号：US20110273266A1

公开(公告)日：2011-11-10

申请号：US12923574

申请日：2010-09-28

申请人： Mi Jin Park ,  Young Do Kweon ,  Jin Gu Kim

发明人： Mi Jin Park ,  Young Do Kweon ,  Jin Gu Kim

IPC分类号： H01C1/012 ,  H01C17/06

CPC分类号： H01C7/003 ,  H01C1/01 ,  H01C7/06 ,  Y10T29/49082 ,  Y10T29/49099

摘要： There are provided a resistor and a method of fabricating the same. More particularly, there are provided a resistor having a parallel structure capable of easily implementing a resistance value when forming a resistor directly on a wafer during a wafer process, and a method of fabricating the same.The resistor includes: a substrate; a lower resistant material layer formed on the upper portion of the substrate; an insulating layer to be stacked on the upper portion of the lower resistant material layer; an upper resistant material layer to be stacked on the upper portion of the insulating layer; and two penetration parts vertically penetrating through the insulating layer, wherein the penetration part is filled with a resistant material having the same component as that of the lower resistant material layer and the upper resistant material layer to electrically connect the upper resistant material layer to the lower resistant material layer.

摘要翻译： 提供了一种电阻器及其制造方法。 更具体地说，提供了一种具有平行结构的电阻器及其制造方法，该并联结构能够在晶片工艺期间直接在晶片上形成电阻时容易地实现电阻值。 电阻器包括：基板; 在所述基板的上部形成有较低阻力的材料层; 绝缘层，堆叠在下阻抗材料层的上部; 层叠在绝缘层的上部的上部电阻材料层; 和穿过绝缘层的两个穿透部分，其中穿透部分填充有与下阻力材料层和上阻力材料层具有相同成分的电阻材料，以将上部阻力材料层与下部电阻材料层电连接 耐材料层。

公开(公告)号：US20110269413A1

公开(公告)日：2011-11-03

申请号：US12926280

申请日：2010-11-05

申请人： Seung Wook Park ,  Young Do Kweon ,  Mi Jin Park

发明人： Seung Wook Park ,  Young Do Kweon ,  Mi Jin Park

IPC分类号： H04B1/38 ,  H05K3/30

CPC分类号： H05K1/16 ,  H05K3/284 ,  H05K3/4629 ,  Y10T29/4913

摘要： There are provided a circuit board and a method for manufacturing the same. The circuit board according to the present invention includes: a first wiring pattern that is formed on one surface of the board; a second wiring pattern that is formed on the other surface of the board; an RF transmitter that is formed on one surface of the board and is connected to the first wiring pattern; and an RF receiver that is formed on the other surface of the board to be paired with the RF transmitter and is connected to the second wiring pattern, wherein the first wiring pattern and the second wiring pattern are electrically connected to each other by wireless communication from the RF transmitter to the RF receiver.

摘要翻译： 提供了一种电路板及其制造方法。 根据本发明的电路板包括：形成在板的一个表面上的第一布线图案; 形成在所述板的另一个表面上的第二布线图案; RF发射器，其形成在所述板的一个表面上并连接到所述第一布线图案; 以及RF接收器，其形成在所述板的另一表面上以与所述RF发射器配对并且连接到所述第二布线图案，其中所述第一布线图案和所述第二布线图案通过无线通信彼此电连接， RF发射机到RF接收机。

公开(公告)号：US20110201156A1

公开(公告)日：2011-08-18

申请号：US13064878

申请日：2011-04-22

申请人： Jin Gu Kim ,  Young Do Kweon ,  Hyung Jin Jeon ,  Seung Wook Park ,  Hee Kon Lee ,  Seon Hee Moon

发明人： Jin Gu Kim ,  Young Do Kweon ,  Hyung Jin Jeon ,  Seung Wook Park ,  Hee Kon Lee ,  Seon Hee Moon

IPC分类号： H01L21/50

CPC分类号： H01L21/561 ,  H01L23/24 ,  H01L23/3121 ,  H01L24/94 ,  H01L2924/09701 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00

摘要： A method of manufacturing a wafer level package including: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant and cutting a wafer level package along the dicing lines coated with the resin into units.

摘要翻译： 一种制造晶片级封装的方法，包括：准备包括形成在底表面上的多个焊盘，位于顶表面上的多个芯片的基板晶片和用于分割芯片的切割线; 在焊盘上形成外部连接单元; 通过将衬底定位在衬底晶片上以仅露出切割线，在切割线上涂覆树脂; 去除面具; 通过用密封剂涂覆芯片来封装位于树脂之间的芯片，并沿着涂覆有树脂的切割线将晶片级封装切割成单元。

公开(公告)号：US07947530B2

公开(公告)日：2011-05-24

申请号：US12453273

申请日：2009-05-05

申请人： Jin Gu Kim ,  Young Do Kweon ,  Hyung Jin Jeon ,  Seung Wook Park ,  Hee Kon Lee ,  Seon Hee Moon

发明人： Jin Gu Kim ,  Young Do Kweon ,  Hyung Jin Jeon ,  Seung Wook Park ,  Hee Kon Lee ,  Seon Hee Moon

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L21/561 ,  H01L23/24 ,  H01L23/3121 ,  H01L24/94 ,  H01L2924/09701 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00

摘要： The present invention relates to a method of manufacturing a wafer level package including the steps of: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant; removing the resin coated on the dicing lines; and cutting a wafer level package along the dicing lines exposed by removing the resin into units.

摘要翻译： 本发明涉及一种制造晶片级封装的方法，包括以下步骤：制备包括形成在底表面上的多个焊盘，位于顶表面上的多个芯片的基板晶片和用于分割芯片的切割线 ; 在焊盘上形成外部连接单元; 通过将衬底定位在衬底晶片上以仅露出切割线，在切割线上涂覆树脂; 去除面具; 通过用密封剂涂覆芯片来封装位于树脂之间的芯片; 去除涂覆在切割线上的树脂; 以及沿着通过将树脂去除单元暴露的切割线切割晶片级封装。

公开(公告)号：US20110108993A1

公开(公告)日：2011-05-12

申请号：US12805334

申请日：2010-07-26

申请人： Joon Seok Kang ,  Young Do Kweon ,  Seung Wook Park ,  Jong Yun Lee ,  Kyung Seob Oh

发明人： Joon Seok Kang ,  Young Do Kweon ,  Seung Wook Park ,  Jong Yun Lee ,  Kyung Seob Oh

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L23/5389 ,  H01L23/49827 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/0231 ,  H01L2224/24226 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/185 ,  H05K2201/10674 ,  H05K2203/1469 ,  H01L2924/00

摘要： There is provided a semiconductor package including: a circuit board having a receiving space formed therein; a semiconductor chip inserted into the receiving space of the circuit board; and an electrode pattern portion having a pattern shape on one surface of the semiconductor chip, and directly contacting a via portion of the circuit board so as to be electrically connected thereto.

摘要翻译： 提供一种半导体封装，包括：电路板，其中形成有容纳空间; 插入电路板的接收空间中的半导体芯片; 以及在半导体芯片的一个表面上具有图案形状的电极图形部分，并且与电路板的通孔部分直接接触以与其电连接。

公开(公告)号：US20110048778A1

公开(公告)日：2011-03-03

申请号：US12654306

申请日：2009-12-16

申请人： Jong Woo Han ,  Soon Gvu Yim ,  Young Do Kweon

发明人： Jong Woo Han ,  Soon Gvu Yim ,  Young Do Kweon

IPC分类号： H05K1/16 ,  H05K1/11 ,  H05K3/10

CPC分类号： H05K3/305 ,  H01L21/563 ,  H01L23/49894 ,  H01L2224/29012 ,  H01L2224/73203 ,  H01L2224/81191 ,  H01L2224/83192 ,  H01L2924/09701 ,  H05K3/3436 ,  H05K3/3452 ,  H05K3/3494 ,  H05K2201/10977 ,  Y02P70/613 ,  Y10T29/49155

摘要： A circuit board includes a board part including a pattern portion on one surface thereof, the pattern portion being electrically connected to a semiconductor chip, and an under-fill layer disposed on the board part and exposing the pattern portion to the outside, the under-fill layer flowing to cover the pattern portion by heat generated in mounting the semiconductor chip.

摘要翻译： 电路板包括一个板部分，其一个表面上包括一个图形部分，该图形部分电连接到一个半导体芯片上，一个底部填充层设置在该板部分上，并将图形部分暴露于外部， 填充层通过在安装半导体芯片时产生的热量流动以覆盖图案部分。

公开(公告)号：US07749882B2

公开(公告)日：2010-07-06

申请号：US11509441

申请日：2006-08-23

申请人： Young Do Kweon ,  Tongbi Jiang

发明人： Young Do Kweon ,  Tongbi Jiang

IPC分类号： H01L21/44

CPC分类号： H01L24/742 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/566 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/544 ,  H01L24/11 ,  H01L24/12 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54486 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/11013 ,  H01L2224/11015 ,  H01L2224/1183 ,  H01L2224/1184 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/7598 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/384 ,  H01L2924/00 ,  H01L2224/05599

摘要： Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed.

摘要翻译： 本文公开了在半导体工件上形成多个微电子器件的微电子器件和方法。 一种这样的方法包括将多个第一互连元件放置在半导体工件的一侧上，在工件侧面上形成层，通过加热第一互连元件来重塑第一互连元件，以及将多个第一互连元件的第一部分 单独的第二互连元件到相应的第一互连元件，其中所述单个第二互连元件的第二部分被暴露。

公开(公告)号：US20100144152A1

公开(公告)日：2010-06-10

申请号：US12453274

申请日：2009-05-05

申请人： Seung Wook Park ,  Jin Gu Kim ,  Jong Hwan Baek ,  Jong Yun Lee ,  Hyung Jin Jeon ,  Young Do Kweon

发明人： Seung Wook Park ,  Jin Gu Kim ,  Jong Hwan Baek ,  Jong Yun Lee ,  Hyung Jin Jeon ,  Young Do Kweon

IPC分类号： H01L21/302

CPC分类号： H01L21/4832 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/5389 ,  H01L2224/12105 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2224/0401

摘要： The present invention relates to a method of manufacturing a semiconductor package capable of simplifying a process and remarkably reducing a production cost by including the steps of: preparing a different bonded panel including at least one metal layer; forming a pad unit electrically connected to the metal layer; mounting a semiconductor chip over the different bonded panel to be electrically connected to the pad unit; sealing the semiconductor chip; forming a rearrangement wiring layer by etching the metal layer; and forming an external connection unit electrically connected to the rearrangement wiring layer.

摘要翻译： 本发明涉及一种制造半导体封装的方法，其能够简化工艺并显着降低生产成本，包括以下步骤：制备包括至少一个金属层的不同键合板; 形成电连接到所述金属层的焊盘单元; 将半导体芯片安装在所述不同的接合面板上以电连接到所述焊盘单元; 密封半导体芯片; 通过蚀刻金属层形成重排布线层; 以及形成与所述重排布线层电连接的外部连接单元。