公开(公告)号：US20240282842A1

公开(公告)日：2024-08-22

申请号：US18636401

申请日：2024-04-16

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jean-Pierre Colinge ,  Carlos H. Diaz

IPC分类号： H01L29/66 ,  B82Y10/00 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/66742 ,  B82Y10/00 ,  H01L21/823487 ,  H01L21/823885 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532

摘要： According to another embodiment, a method of forming a transistor is provided. The method includes the following operations: providing a substrate; providing a source over the substrate; providing a channel connected to the source; providing a drain connected to the channel; providing a gate insulator adjacent to the channel; providing a gate adjacent to the gate insulator; providing a first interlayer dielectric between the source and the gate; and providing a second interlayer dielectric between the drain and the gate, wherein at least one of the formation of the source, the drain, and the channel includes about 20-95 atomic percent of Sn.

公开(公告)号：US12068412B2

公开(公告)日：2024-08-20

申请号：US17545265

申请日：2021-12-08

申请人： HYUNDAI MOBIS Co., Ltd.

发明人： Sin A Kim ,  Tae Youp Kim ,  Jeong Mok Ha ,  Hyuk Woo

IPC分类号： H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16

CPC分类号： H01L29/7813 ,  H01L27/088 ,  H01L29/0657 ,  H01L29/0865 ,  H01L29/1608

摘要： A power semiconductor device according to an aspect of the present disclosure includes a semiconductor layer of silicon carbide (SiC), a plurality of well regions that is disposed in the semiconductor layer, spaced from each other and has a second conductivity type, a plurality of source regions that are disposed in the semiconductor layer on the plurality of well regions respectively, spaced from each other, a drift region that has the first conductivity type and is disposed in the semiconductor layer, the drift region extending from a lower side of the plurality of well regions to a surface of the semiconductor layer through between the plurality of well regions, a plurality of trenches, a gate insulating layer, and a gate electrode layer that is disposed on the gate insulating layer.

公开(公告)号：US12068400B2

公开(公告)日：2024-08-20

申请号：US17737003

申请日：2022-05-04

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chun-Tsung Kuo ,  Chuan-Feng Chen

IPC分类号： H01L29/732 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/732 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66272

摘要： A BJT and methods of forming the same are described. The BJT includes a collector region disposed in a substrate, a lower base structure disposed on the collector region, a first dielectric layer surrounding a bottom portion of the lower base structure, and a second dielectric layer surrounding a top portion of the lower base structure. The first dielectric layer includes a first oxide, the second dielectric layer includes a second oxide, and the first and second oxides have different densities. The BJT further includes an upper base structure disposed on the second dielectric layer and the lower base structure, an emitter region disposed on the lower base structure, a sidewall spacer structure disposed between the emitter region and the upper base structure, and the sidewall spacer structure includes a material different from materials of the first and second dielectric layers.

公开(公告)号：US12068382B2

公开(公告)日：2024-08-20

申请号：US17728679

申请日：2022-04-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC分类号： H01L29/417 ,  H01L21/768 ,  H01L23/522 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L21/76877 ,  H01L23/5226 ,  H01L29/0847 ,  H01L29/785

摘要： A semiconductor structure includes a substrate; a first structure over the substrate and having a first gate stack and two first gate spacers on two opposing sidewalls of the first gate stack; a second structure over the substrate and having a second gate stack and two second gate spacers on two opposing sidewalls of the second gate stack; a source/drain (S/D) feature over the substrate and adjacent to the first and the second gate stacks; an S/D contact over the S/D feature and between one of the first gate spacers and one of the second gate spacers; a conductive via disposed over and electrically connected to the S/D contact; and a dielectric liner layer. A first portion of the dielectric liner layer is disposed on a sidewall of the one of the first gate spacers and is directly above the S/D contact and spaced from the S/D contact.

公开(公告)号：US12068155B2

公开(公告)日：2024-08-20

申请号：US17396371

申请日：2021-08-06

申请人： Applied Materials, Inc.

发明人： Chen-Ying Wu ,  Zhiyuan Ye ,  Xuebin Li ,  Sathya Chary ,  Yi-Chiau Huang ,  Saurabh Chopra

IPC分类号： H01L21/02 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/04

CPC分类号： H01L21/02211 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/04

摘要： Embodiments described herein relate to a method of epitaxial deposition of p-channel metal oxide semiconductor (MMOS) source/drain regions within horizontal gate all around (hGAA) device structures. Combinations of precursors are described herein, which grow of the source/drain regions on predominantly surfaces with reduced or negligible growth on surfaces. Therefore, growth of the source/drain regions is predominantly located on the top surface of a substrate instead of the alternating layers of the hGAA structure. The precursor combinations include a silicon containing precursor, a germanium containing precursor, and a boron containing precursor. At least one of the precursors further includes chlorine.

公开(公告)号：US20240274716A1

公开(公告)日：2024-08-15

申请号：US18324238

申请日：2023-05-26

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Hsin Fu Lin ,  Shiang-Hung Huang ,  Pei-Shan Hsieh

IPC分类号： H01L29/78 ,  H01L21/265 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L21/26506 ,  H01L29/0649 ,  H01L29/086 ,  H01L29/1041 ,  H01L29/42368 ,  H01L29/66689 ,  H01L29/66803

摘要： A field effect transistor includes a source-side doped well, a drift-region well, a source region, a drain region; a shallow trench isolation structure including a first portion overlying the drift-region well and laterally spaced from the source-side doped well; a gate dielectric layer; a gate electrode overlying the gate dielectric layer; and a proximal doped layer stack embedded within the drift-region well and interposed between the source-side doped well and the first portion of the shallow trench isolation structure. Proximal doped semiconductor layers of the proximal doped layer stack have different average atomic concentrations of dopants of the second conductivity type.

公开(公告)号：US20240274670A1

公开(公告)日：2024-08-15

申请号：US18642509

申请日：2024-04-22

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Yoshiki YAMAMOTO ,  Hideki MAKIYAMA ,  Toshiaki IWAMATSU ,  Takaaki TSUNOMURA

IPC分类号： H01L29/10 ,  H01L21/265 ,  H01L21/74 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/1083 ,  H01L21/265 ,  H01L21/74 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/41783 ,  H01L29/4238 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/6681 ,  H01L29/7824 ,  H01L29/7833 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78651 ,  H01L29/78654

摘要： Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

公开(公告)号：US20240274667A1

公开(公告)日：2024-08-15

申请号：US18644770

申请日：2024-04-24

申请人： Taiwan Semiconductor Manufacturing co., Ltd

发明人： Heng-Wen Ting ,  Kei-Wei Chen ,  Chii-Horng Li ,  Pei-Ren Jeng ,  Hsueh-Chang Sung ,  Yen-Ru Lee ,  Chun-An Lin

IPC分类号： H01L29/08 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L21/02532 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/785

摘要： A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching one or more semiconductor fins to form one or more recesses; and forming a source/drain region in the one or more recesses, the forming the source/drain region including epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material including doped silicon germanium and having a different composition than the first semiconductor material.

公开(公告)号：US20240274663A1

公开(公告)日：2024-08-15

申请号：US18641408

申请日：2024-04-21

申请人： FUJI ELECTRIC CO., LTD.

发明人： Tohru SHIRAKAWA ,  Kaname MITSUZUKA

IPC分类号： H01L29/08 ,  H01L27/06 ,  H01L29/06 ,  H01L29/739 ,  H01L29/861

CPC分类号： H01L29/0821 ,  H01L27/0664 ,  H01L29/0623 ,  H01L29/7397 ,  H01L29/8613

摘要： Provided is a semiconductor device including: a semiconductor substrate provided with a drift region of a first conductivity type; an emitter region of the first conductivity type provided in contact with an upper surface of the semiconductor substrate and having a higher doping concentration than the drift region; a base region of a second conductivity type provided in contact with the emitter region; a collector region of the second conductivity type provided between the drift region and a lower surface of the semiconductor substrate; and a floating region of the first conductivity type provided in contact with an upper surface of the collector region and having a higher doping concentration than the collector region, wherein the collector region has a first region which is not covered with the floating region and a second region which is covered with the floating region.

公开(公告)号：US20240274597A1

公开(公告)日：2024-08-15

申请号：US18320724

申请日：2023-05-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Lin HSU ,  Yu-Ti Su

IPC分类号： H01L27/02 ,  H01L21/8249 ,  H01L29/08

CPC分类号： H01L27/0292 ,  H01L21/8249 ,  H01L27/0274 ,  H01L29/0847 ,  H01L27/0207

摘要： A circuit includes a substrate, p-well regions over the substrate and including n- channel metal-oxide semiconductor field-effect transistors, n-well regions over the substrate and including p-channel metal-oxide semiconductor field-effect transistors, drain/source regions of protection metal-oxide semiconductor field-effect transistors, and at least one control circuit. First conductive connections connect selected drain/source regions to the p-well regions and the n-well regions, second conductive connections connect selected n-channel metal-oxide semiconductor field-effect transistors and p-channel metal-oxide semiconductor field-effect transistors to one another, and third conductive connections are configured to connect gates of the protection metal-oxide semiconductor field-effect transistors to the at least one control circuit.