公开(公告)号：US20180081563A1

公开(公告)日：2018-03-22

申请号：US15272894

申请日：2016-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts

IPC: G06F3/06

CPC classification number: G11C7/00 ,  G11C7/222 ,  G11C2029/0409

Abstract: Logic such as a memory controller writes primary data from an incoming write request as well as corresponding replicated primary data (which is a copy of the primary data) to one or more different memory banks of random access memory in response to determining a memory access contention condition for the address (including a range of addresses) corresponding to the incoming write request. When the memory bank containing the primary data is busy servicing a write request, such as to another row of memory in the bank, a read request for the primary data is serviced by reading the replicated primary data from the different memory bank of the random access memory to service the incoming read request.

公开(公告)号：US09924176B2

公开(公告)日：2018-03-20

申请号：US14879616

申请日：2015-10-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Andrew S. C. Pomianowski ,  Konstantine Iourcha

IPC: G06K9/00 ,  H04N19/176 ,  G06T1/60 ,  H04N19/46 ,  H04N19/12

CPC classification number: H04N19/176 ,  G06T1/60 ,  H04N1/41 ,  H04N19/12 ,  H04N19/46

Abstract: A method and apparatus is provided for block based compression of a texture using hardware supported compression formats. The method comprises dividing a texture into a plurality of blocks, for each block, determining a transform for use with the block to minimize an error metric, encoding at least one characteristic of the transform into a plurality of bits otherwise available to represent reference component values, and compressing the block.

公开(公告)号：US09921635B2

公开(公告)日：2018-03-20

申请号：US14068207

申请日：2013-10-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko Eckert ,  Manish Arora

IPC: G06F1/32

CPC classification number: G06F1/3228 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3231 ,  G06F1/324 ,  G06F1/3246 ,  Y02D10/126 ,  Y02D10/173

Abstract: An approach is described herein that includes a method for power management of a device. In one example, the method includes sampling duration characteristics for a plurality of past idle events for a predetermined interval of time and determining whether to transition a device to a powered-down state based on the sampled duration characteristics. In another example, the method includes determining whether an average idle time for a plurality of past idle events exceeds an energy break-even point threshold. If the average idle time for the plurality of past idle events exceeds the energy break-even point threshold, a device is immediately transitioned to a powered-down state upon receipt of a next idle event. If the average idle time for the plurality of past idle events does not exceed the energy break-even point threshold, transition of the device to the powered-down state is delayed.

公开(公告)号：US20180074977A1

公开(公告)日：2018-03-15

申请号：US15267094

申请日：2016-09-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Gregory W. Smaus ,  John M. King ,  Michael D. Achenbach ,  Kevin M. Lepak ,  Matthew A. Rafacz ,  Noah Bamford

IPC: G06F12/14 ,  G06F9/52 ,  G06F9/30

CPC classification number: G06F12/1466 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/528 ,  G06F2212/1052

Abstract: Techniques for improving execution of a lock instruction are provided herein. A lock instruction and younger instructions are allowed to speculatively retire prior to the store portion of the lock instruction committing its value to memory. These instructions thus do not have to wait for the lock instruction to complete before retiring. In the event that the processor detects a violation of the atomic or fencing properties of the lock instruction prior to committing the value of the lock instruction, the processor rolls back state and executes the lock instruction in a slow mode in which younger instructions are not allowed to retire until the stored value of the lock instruction is committed. Speculative retirement of these instructions results in increased processing speed, as instructions no longer need to wait to retire after execution of a lock instruction.

公开(公告)号：US09916189B2

公开(公告)日：2018-03-13

申请号：US14479297

申请日：2014-09-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Martin T. Pohlack ,  Stephan Diestelhorst

IPC: G06F9/52 ,  G06F12/06 ,  G06F9/45 ,  G06F12/0855

CPC classification number: G06F9/52 ,  G06F8/458 ,  G06F12/0857 ,  G06F2201/825

Abstract: In the described embodiments, entities in a computing device selectively write specified values to a lock variable in a local cache and one or more lower levels of a memory hierarchy to enable multiple entities to enable the concurrent execution of corresponding critical sections of program code that are protected by a same lock.

公开(公告)号：US20180067856A1

公开(公告)日：2018-03-08

申请号：US15256950

申请日：2016-09-06

Applicant: Advanced Micro Devices, Inc.

Inventor： William L. Walker

IPC: G06F12/0811 ,  G06F12/128 ,  G06F12/0831

CPC classification number: G06F12/128 ,  G06F2212/283 ,  G06F2212/69 ,  G06F2212/70

Abstract: A system for managing cache utilization includes a processor core, a lower-level cache, and a higher-level cache. In response to activating the higher-level cache, the system counts lower-level cache victims evicted from the lower-level cache. While a count of the lower-level cache victims is not greater than a threshold number, the system transfers each lower-level cache victim to a system memory without storing the lower-level cache victim to the higher-level cache. When the count of the lower-level cache victims is greater than the threshold number, the system writes each lower-level cache victim to the higher-level cache. In this manner, if the higher-level cache is deactivated before the threshold number of lower-level cache victims is reached, the higher-level cache is empty and thus may be deactivated without flushing.

公开(公告)号：US09910788B2

公开(公告)日：2018-03-06

申请号：US14861055

申请日：2015-09-22

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Philip J. Rogers ,  Benjamin T. Sander ,  Anthony Asaro

IPC: G06F12/121 ,  G06F12/0891 ,  G06F12/1081 ,  G06F13/28 ,  G06F12/12

CPC classification number: G06F12/121 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/1081 ,  G06F12/12 ,  G06F12/127 ,  G06F13/28 ,  G06F2212/656

Abstract: A processor device includes a cache and a memory storing a set of counters. Each counter of the set is associated with a corresponding block of a plurality of blocks of the cache. The processor device further includes a cache access monitor to, for each time quantum for a series of one or more time quanta, increment counter values of the set of counters based on accesses to the corresponding blocks of the cache. The processor device further includes a transfer engine to, after completion of each time quantum, transfer the counter values of the set of counters for the time quantum to a corresponding location in a system memory.

公开(公告)号：US09910605B2

公开(公告)日：2018-03-06

申请号：US15353431

申请日：2016-11-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Nuwan S. Jayasena ,  Gabriel H. Loh ,  James M. O'Connor ,  Niladrish Chatterjee

IPC: G06F3/06 ,  G06F12/06 ,  G06F12/0811

CPC classification number: G06F3/0613 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0647 ,  G06F3/0685 ,  G06F12/0292 ,  G06F12/0638 ,  G06F12/0811 ,  G06F12/0897 ,  G06F2212/205 ,  G11C11/005 ,  Y02D10/13

Abstract: A die-stacked hybrid memory device implements a first set of one or more memory dies implementing first memory cell circuitry of a first memory architecture type and a second set of one or more memory dies implementing second memory cell circuitry of a second memory architecture type different than the first memory architecture type. The die-stacked hybrid memory device further includes a set of one or more logic dies electrically coupled to the first and second sets of one or more memory dies, the set of one or more logic dies comprising a memory interface and a page migration manager, the memory interface coupleable to a device external to the die-stacked hybrid memory device, and the page migration manager to transfer memory pages between the first set of one or more memory dies and the second set of one or more memory dies.

公开(公告)号：US09898568B2

公开(公告)日：2018-02-20

申请号：US14748075

申请日：2015-06-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Naveen Chandra Srivastava ,  Janardhan Achanta ,  Pankaj Kumar ,  Shreekanth Karandoor Sampigethaya

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5081 ,  G06F2217/78

Abstract: Systems, apparatuses, and methods for reducing the load on the bitlines of a ROM bitcell array are described. The connections between nets of a ROM bitcell array may be assigned based on their programmed values using a traditional approach. Then, a plurality of optimizations may be performed on the assignment of nets to reduce the load on the bitlines of the array. A first optimization may swap the connections between ground and bitline for the nets of a given column responsive to detecting that the number of connections to the corresponding bitline is greater than the number of connections to ground for the given column. A second optimization may remove the connection of a net to a bitline if three consecutive nets of a given column are connected to the bitline.

公开(公告)号：US09898287B2

公开(公告)日：2018-02-20

申请号：US14682971

申请日：2015-04-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Sooraj Puthoor ,  Bradford M. Beckmann ,  Dmitri Yudanov

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/46

CPC classification number: G06F9/30058 ,  G06F9/3804 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/46

Abstract: A method, a non-transitory computer readable medium, and a processor for repacking dynamic wavefronts during program code execution on a processing unit, each dynamic wavefront including multiple threads are presented. If a branch instruction is detected, a determination is made whether all wavefronts following a same control path in the program code have reached a compaction point, which is the branch instruction. If no branch instruction is detected in executing the program code, a determination is made whether all wavefronts following the same control path have reached a reconvergence point, which is a beginning of a program code segment to be executed by both a taken branch and a not taken branch from a previous branch instruction. The dynamic wavefronts are repacked with all threads that follow the same control path, if all wavefronts following the same control path have reached the branch instruction or the reconvergence point.