公开(公告)号：US10290726B2

公开(公告)日：2019-05-14

申请号：US15548290

申请日：2016-01-28

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Yan Gu ,  Wei Su ,  Sen Zhang

IPC: H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/735 ,  H01L29/739

Abstract: A lateral insulated gate bipolar transistor, comprising: a substrate (100), having a first conductivity type; an insulating layer (200), formed on the substrate (100); an epitaxial layer (300), having a second conductivity type and formed on the insulating layer (200); a field oxide layer (400), formed on the epitaxial layer (300); a first well (500), having the first conductivity type; a plurality of gate trench structures (600); second source doped regions (720), having the second conductivity type; first source doped regions (710), having the first conductivity type; a second well (800), having the second conductivity type; a first drain doped region (910), having the first conductivity type and formed on a surface layer of the second well (800); gate lead-out ends (10); a source lead-out end (20); a drain lead-out end (30).

公开(公告)号：US10290705B2

公开(公告)日：2019-05-14

申请号：US15564181

申请日：2016-01-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Feng Huang ,  Guangtao Han ,  Guipeng Sun ,  Feng Lin ,  Longjie Zhao ,  Huatang Lin ,  Bing Zhao

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/76 ,  H01L29/06 ,  H01L21/762

Abstract: Provided are a laterally diffused metal oxide semiconductor field-effect transistor and a manufacturing method therefor. The method comprises: providing a wafer on which a first N well (22), a first P well (24) and a channel region shallow trench isolating structure (42) are formed; forming a high-temperature oxidation film on the surface of the wafer by deposition; photoetching and dryly etching the high-temperature oxidation film, and reserving a thin layer as an etching buffer layer; performing wet etching, removing the etching buffer layer in a region which is not covered by a photoresist, and forming a mini oxidation layer (52); performing photoetching and ion injection to form a second N well (32) in the first N well and form a second P well (34) in the first P well; forming a polysilicon gate (62) and a gate oxide layer on the surface of the wafer; and photoetching and injecting N-type ions to form a drain electrode (72) and a source electrode (74).

公开(公告)号：US10199495B2

公开(公告)日：2019-02-05

申请号：US15766082

申请日：2016-08-18

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shukun Qi ,  Guipeng Sun

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06

Abstract: A laterally diffused metal-oxide semiconductor field-effect transistor, comprising a substrate, a first conductivity type well region, a second conductivity type well region, a drain electrode in the first conductivity type well region, a source electrode and a body region in the second conductivity type well region, and a gate electrode arranged across surfaces of the first conductivity type well region and the second conductivity type well region, and also comprising a floating layer ring arranged on the top of the first conductivity type well region and located between the gate electrode and the drain electrode and a plurality of groove polysilicon electrodes running through the floating layer ring and stretching into the first conductivity type well region.

公开(公告)号：US20180224281A1

公开(公告)日：2018-08-09

申请号：US15747882

申请日：2016-05-11

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huagang WU ,  Xueyan WANG

IPC: G01C19/5776 ,  G01P15/12 ,  G01P15/18

CPC classification number: G01C19/5776 ,  G01P15/0802 ,  G01P15/12 ,  G01P15/18 ,  G05B2219/36159

Abstract: An accelerator comprises: an accelerometer (100), configured to detect an acceleration of a motion of a carrier and output a corresponding electrical signal; a sampling and low-pass filter (200), coupled to the accelerometer (100), and configured to sample the electrical signal regularly and filter a noise from the electrical signal; an amplifier (300), configured to amplify the electrical signal after filtering the noise; an analog-to-digital converter (400), configured to convert the amplified electrical signal into a digital signal; a function control module (500), configured to process the digital signal and output a control signal to control the analog-to-digital converter (400), the amplifier (300), and the sampling and low-pass filter (200); and an oscillator module (600), configured to output, according to the control signal, a sampling signal to the sampling and low-pass filter (200), so as to control the sampling and low-pass filter (200) to sample the electrical signal regularly.

公开(公告)号：US09977342B2

公开(公告)日：2018-05-22

申请号：US15315168

申请日：2015-06-26

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Zhenhai Yao

IPC: G03F9/00 ,  G03F7/20

CPC classification number: G03F7/70633 ,  G03F1/00 ,  G03F1/38 ,  G03F7/70775 ,  G03F9/7003 ,  G03F9/7019 ,  G03F9/7046 ,  G03F9/7069

Abstract: A lithography stepper alignment and control method, comprising: providing a test template having a plurality of field sizes, and deriving a set of overlay values for each field size (S1); calculating a set of compensation amounts for the overlay value of each field size (S2); and, comparing a set of estimated alignment compensation values for a product with each compensation amount for each field size, selecting as the product alignment compensation values the set of compensation amounts of a field size closest to the set of estimated alignment compensation values, and, using the product alignment compensation values to perform alignment compensation on said product (S3).

公开(公告)号：US20180122921A1

公开(公告)日：2018-05-03

申请号：US15564172

申请日：2016-01-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shukun QI ,  Guangsheng ZHANG ,  Guipeng SUN ,  Sen ZHANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66681 ,  H01L29/06 ,  H01L29/063 ,  H01L29/7816

Abstract: Provided is a laterally diffused metal-oxide-semiconductor field-effect transistor, comprising a substrate (110), a source (150), a drain (140), a body region (160), a P-type field-limiting ring (135), and a well region on the substrate (110); the well region comprises an inserted well (122), which has P-type doping and is disposed below the drain and connected to the drain; N wells (124) disposed at the two sides of the inserted well (122); a P well (126) disposed next to the N well (124) and connected to the N well (124); a P-type field-limiting ring (135), which is disposed inside the N well (124), is a closed ring-shaped structure, and is located at the periphery below the drain (140); the inserted well (122) extends in its longitudinal direction to the position where it is in contact with said P-type field-limiting ring (135); the source (150) and the body region (160) are disposed inside the P well (126).

公开(公告)号：US20180012890A1

公开(公告)日：2018-01-11

申请号：US15547239

申请日：2015-09-23

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Wei LI ,  Long HAO ,  Yan JIN ,  Dejin WANG

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  H01L29/45 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L27/0922 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823462 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/088 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66492 ,  H01L29/66515 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7831

Abstract: A manufacturing method of a semiconductor device, comprising the following steps: providing a semiconductor substrate comprising a low-voltage device region and a high-voltage device region; forming first gate oxide layers in a non-gate region of the high-voltage device region and the low-voltage device region and a second gate oxide layer in a gate region of the high-voltage device region; the thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer; forming a first polysilicon gate and a first sidewall structure on the surface of the first gate oxide layer of the low-voltage device region and a second polysilicon gate and a second sidewall structure on the surface of the second gate oxide layer; the width of the second gate oxide layer is greater than the width of the second polysilicon gate; performing source drain ions injection to form a source drain extraction region; after depositing a metal silicide area block (SAB), performing a photolithographic etching on the metal SAB and forming metal silicide. The above manufacturing method of a semiconductor device simplifies process steps and reduces process cost. The present invention also relates to a semiconductor device.

公开(公告)号：US09778577B2

公开(公告)日：2017-10-03

申请号：US14762837

申请日：2013-12-31

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Wei Huang

IPC: G03F7/20 ,  H01L23/544 ,  G01B11/02 ,  H01L21/66

CPC classification number: G03F7/70625 ,  G01B11/02 ,  H01L22/12 ,  H01L23/544

Abstract: A testing structure of a strip width of a scribing slot is provided, the structure includes a first isolated line (232) and a second isolated line (234) which are perpendicular to each other, the testing structure further includes a first field region pattern (220), the first field region pattern (220) includes two graphics, the two graphics are each located on one side of the first isolated line (232) and opposite to each other. A testing method of a strip width of a scribing slot is also disclosed. Graphics of the field oxide region simulating the LOCOS structure are provided on two sides of the isolated line, the step is artificially generated, a polysilicon gate graphic on a small size source region formed by photolithography can be displayed through online testing of the strip width or online displaying and checking of the strip width, thus a practical situation of the die can be known, an abnormity of the strip width and morphology of the polysilicon gate caused by a reflection of a substrate can be found instantly.

公开(公告)号：US09754795B2

公开(公告)日：2017-09-05

申请号：US15120323

申请日：2015-04-30

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Qiang Hua ,  Yaohui Zhou

IPC: H01L21/02 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L21/31056 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3081 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76 ,  H01L21/762

Abstract: A chemical-mechanical polishing process using a silicon oxynitride anti-reflection layer (S340) includes: (S1) providing a semiconductor wafer comprising a substrate (S310), an oxidation layer (S320) formed on the substrate (S310), a silicon nitride layer (S330) formed on the oxidation layer (S320), an anti-reflection layer (S340) formed on the silicon nitride layer (S330), a trench extending through the anti-reflection layer (S340) and into the substrate (S310), and a first silicon dioxide layer (S350) filling the trench and covering the anti-reflection layer (S340); (S2) polishing the first silicon dioxide layer (S350) until the anti-reflection layer (S340) is exposed; (S3) removing the anti-reflection layer (S340) by dry etching; (S4) forming a second silicon dioxide layer (S360) on the surface of the semiconductor wafer from which the anti-reflection layer (S340) is removed; (S5) polishing the second silicon dioxide layer (S360) until the silicon nitride layer (S330) is exposed; (S6) and, removing the silicon nitride layer (S330).

公开(公告)号：US09696371B2

公开(公告)日：2017-07-04

申请号：US14759370

申请日：2013-12-31

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Ming Wang ,  Xiaoqian Lian ,  Yaojun Lin ,  Wenhui Xu ,  Hanshun Chen

IPC: G01R31/02 ,  G01R31/26

CPC classification number: G01R31/2621 ,  G01R31/2623

Abstract: A test method and system for cut-in voltage. The method comprises: coarse scanning of the cut-in voltage: a grid voltage, i.e., the cut-in voltage, is quickly determined when a drain terminal current is greater than a target current for the first time (100); accurate scanning of the cut-in voltage: a scanning step length is shortened continuously until the scanning step length is shorter than a preset step length, and each time the scanning step length is shortened, the scanning is conducted according to the current shortened scanning step length on the basis of the cut-in voltage determined in the former time, and then the cut-in voltage under the condition of the current shortened scanning step length is determined again (200). The scanning voltage is automatically increased or decreased by the test method and system through adding high resolution and high precision test conversion into a second scanning test, and therefore the testing of the cut-in voltage becomes more efficient and more accurate.