公开(公告)号：US07112837B2

公开(公告)日：2006-09-26

申请号：US11262545

申请日：2005-10-28

Applicant: Sheng Teng Hsu ,  Fengyan Zhang ,  Tingkai Li

Inventor： Sheng Teng Hsu ,  Fengyan Zhang ,  Tingkai Li

IPC: H01L29/76

CPC classification number: H01L27/1159 ,  H01L21/84 ,  H01L27/11502 ,  H01L27/11585

Abstract: An MFIS memory array having a plurality of MFIS memory transistors with a word line connecting a plurality of MFIS memory transistor gates, wherein all MFIS memory transistors connected to a common word line have a common source, each transistor drain serves as a bit output, and all MFIS channels along a word line are separated by a P+ region and are further joined to a P+ substrate region on an SOI substrate by a P+ region is provided. Also provided are methods of making an MFIS memory array on an SOI substrate; methods of performing a block erase of one or more word lines, and methods of selectively programming a bit.

Abstract translation: 一种MFIS存储器阵列，具有多个具有连接多个MFIS存储晶体管栅极的字线的MFIS存储晶体管，其中连接到公共字线的所有MFIS存储晶体管具有公共源，每个晶体管漏极用作位输出，以及 沿着字线的所有MFIS通道被P +区隔开，并且通过P +区进一步连接到SOI衬底上的P +衬底区域。 还提供了在SOI衬底上制造MFIS存储器阵列的方法; 执行一个或多个字线的块擦除的方法以及有选择地编程位的方法。

公开(公告)号：US07101720B2

公开(公告)日：2006-09-05

申请号：US10801375

申请日：2004-03-15

Applicant: Fengyan Zhang ,  Sheng Teng Hsu

Inventor： Fengyan Zhang ,  Sheng Teng Hsu

IPC: H01L21/00

CPC classification number: H01L28/55 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/65 ,  H01L28/75

Abstract: A method is provided for forming a single-phase c-axis PGO film overlying a Pt metal electrode. Although the method is summarized in the context of a Pt bottom electrode, it has a broader application to other noble metals. The method comprises: forming a bottom electrode mixture of Pt and Pt3O4; forming a single-phase c-axis PGO thin film overlying the bottom electrode; and, forming a top electrode overlying the PGO thin film. Forming a bottom electrode mixture of a Pt and Pt3O4 includes: forming a Pt first layer; and, forming a second layer, interposed between the first layer and the PGO thin film, of fully oxidized Pt3O4. In other aspects, forming a bottom electrode mixture of Pt and Pt3O4 includes forming a polycrystalline mixture of Pt and Pt3O4. A c-axis PGO film capacitor is also provided. Again, a Pt bottom electrode is described, along with other noble metal bottom electrodes.

Abstract translation: 提供了用于形成覆盖在Pt金属电极上的单相c轴PGO膜的方法。 虽然该方法在Pt底部电极的上下文中总结，但是其更适用于其它贵金属。 该方法包括：形成Pt和Pt 3 O 4的底部电极混合物; 形成覆盖在底部电极上的单相c轴PGO薄膜; 并且形成覆盖PGO薄膜的顶部电极。 形成Pt和Pt 3 N 4 O 4的底部电极混合物包括：形成Pt第一层; 并且形成介于第一层和PGO薄膜之间的完全氧化的Pt 3 O 4 O 4的第二层。 在其它方面，形成Pt和Pt 3 O 4的底部电极混合物包括形成Pt和Pt 3 O 3的多晶混合物 > 4 。 还提供了一个c轴PGO薄膜电容器。 同样地，描述了Pt底部电极以及其它贵金属底部电极。

公开(公告)号：US07098144B2

公开(公告)日：2006-08-29

申请号：US10971280

申请日：2004-10-21

Applicant: Fengyan Zhang ,  Robert A. Barrowcliff ,  Gregory M. Stecker ,  Sheng Teng Hsu

Inventor： Fengyan Zhang ,  Robert A. Barrowcliff ,  Gregory M. Stecker ,  Sheng Teng Hsu

IPC: H01L21/302

CPC classification number: B82Y10/00 ,  B82Y30/00 ,  C30B25/00 ,  C30B29/16 ,  C30B29/605 ,  Y10S977/811 ,  Y10S977/84

Abstract: A method is provided for forming iridium oxide (IrOx) nanotubes. The method comprises: providing a substrate; introducing a (methylcyclopentadienyl)(1,5-cyclooctadiene)iridium(I) precursor; introducing oxygen as a precursor reaction gas; establishing a final pressure in the range of 1 to 50 Torr; establishing a substrate, or chamber temperature in the range of 200 to 500 degrees C.; and using a metalorganic chemical vapor deposition (MOCVD) process, growing IrOx hollow nanotubes from the substrate surface. Typically, the (methylcyclopentadienyl)(1,5-cyclooctadiene)iridium(I) precursor is initially heated in an ampule to a first temperature in the range of 60 to 90 degrees C., and the first temperature is maintained in the transport line introducing the precursor. The precursor may be mixed with an inert carrier gas such as Ar, or the oxygen precursor reaction gas may be used as the carrier.

Abstract translation: 提供了形成氧化铱（IrOx）纳米管的方法。 该方法包括：提供衬底; 引入（甲基环戊二烯基）（1,5-环辛二烯）铱（I）前体; 引入氧气作为前体反应气体; 确定1至50乇范围内的最终压力; 建立基板，或室温在200至500摄氏度的范围内。 并使用金属有机化学气相沉积（MOCVD）工艺，从衬底表面生长IrOx中空纳米管。 通常，（甲基环戊二烯基）（1,5-环辛二烯）铱（I）前体最初在安瓿中加热至60至90℃的第一温度，第一温度保持在输送线 的前身。 前体可以与惰性载气如Ar混合，也可以使用氧前体反应气体作为载体。

公开(公告)号：US20060160304A1

公开(公告)日：2006-07-20

申请号：US11039544

申请日：2005-01-19

Applicant: Sheng Hsu ,  Fengyan Zhang ,  Gregory Stecker ,  Robert Barrowcliff

Inventor： Sheng Hsu ,  Fengyan Zhang ,  Gregory Stecker ,  Robert Barrowcliff

IPC: H01L21/336

CPC classification number: H01L27/101 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1675

Abstract: A non-volatile memory resistor cell with a nanotip electrode, and corresponding fabrication method are provided. The method comprises: forming a first electrode with nanotips; forming a memory resistor material adjacent the nanotips; and, forming a second electrode adjacent the memory resistor material, where the memory resistor material is interposed between the first and second electrodes. Typically, the nanotips are iridium oxide (IrOx) and have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. In one aspect, the substrate material can be silicon, silicon oxide, silicon nitride, or a noble metal. A metalorganic chemical vapor deposition (MOCVD) process is used to deposit Ir. The IrOx nanotips are grown from the deposited Ir.

Abstract translation: 提供了具有纳米尖端电极的非易失性存储器电阻单元及相应的制造方法。 该方法包括：形成具有纳米尖端的第一电极; 在所述纳米尖端附近形成记忆电阻材料; 并且形成与所述存储电阻材料相邻的第二电极，其中所述存储电阻材料置于所述第一和第二电极之间。 通常，纳米针是氧化铱（IrOx），并且具有约50纳米或更小的尖端基底尺寸，在5至50nm范围内的尖端高度，以及每平方微米大于100纳米尖端的纳米密度密度。 一方面，衬底材料可以是硅，氧化硅，氮化硅或贵金属。 使用金属有机化学气相沉积（MOCVD）工艺沉积Ir。 IrOx纳米尖端从沉积的Ir生长。

公开(公告)号：US20060088993A1

公开(公告)日：2006-04-27

申请号：US11013804

申请日：2004-12-15

Applicant: Fengyan Zhang ,  Gregory Stecker ,  Robert Barrowcliff ,  Sheng Hsu

Inventor： Fengyan Zhang ,  Gregory Stecker ,  Robert Barrowcliff ,  Sheng Hsu

IPC: H01L21/4763 ,  H01L21/302

CPC classification number: H01L21/31111 ,  B81C1/00111 ,  B82Y10/00

Abstract: A method is provided for patterning iridium oxide (IrOx) nanostructures. The method comprises: forming a substrate first region adjacent a second region; growing IrOx nanostructures from a continuous IrOx film overlying the first region; simultaneously growing IrOx nanostructures from a non-continuous IrOx film overlying the second region; selectively etching areas of the second region exposed by the non-continuous IrOx film; and, lifting off the IrOx nanostructures overlying the second region. Typically, the first region is formed from a first material and the second region from a second material, different than the first material. For example, the first material can be a refractory metal, or refractory metal oxide. The second material can be SiOx. The step of selectively etching areas of the second region exposed by the non-continuous IrOx film includes exposing the substrate to an etchant that is more reactive with the second material than the IrOx.

Abstract translation: 提供了用于构图氧化铱（IrOx）纳米结构的方法。 该方法包括：在第二区域附近形成衬底第一区域; 从覆盖第一区域的连续IrOx膜生长IrOx纳米结构; 同时从覆盖第二区域的非连续IrOx膜生长IrOx纳米结构; 选择性地蚀刻由非连续IrOx膜暴露的第二区域的区域; 并提升覆盖第二区域的IrOx纳米结构。 通常，第一区域由第一材料形成，第二区域由不同于第一材料的第二材料形成。 例如，第一种材料可以是难熔金属或难熔金属氧化物。 第二种材料可以是SiOx。 选择性地蚀刻由非连续IrOx膜暴露的第二区域的区域的步骤包括将衬底暴露于与IrOx比第二材料更具反应性的蚀刻剂。

公开(公告)号：US20060086314A1

公开(公告)日：2006-04-27

申请号：US10971330

申请日：2004-10-21

Applicant: Fengyan Zhang ,  Robert Barrowcliff ,  Sheng Hsu

Inventor： Fengyan Zhang ,  Robert Barrowcliff ,  Sheng Hsu

IPC: C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC classification number: H01L24/48 ,  C30B25/005 ,  C30B29/16 ,  C30B29/62 ,  H01L24/45 ,  H01L24/49 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/43827 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/45166 ,  H01L2224/45169 ,  H01L2224/45178 ,  H01L2224/45181 ,  H01L2224/45565 ,  H01L2224/45599 ,  H01L2224/45688 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48599 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/14 ,  H01L2924/20751 ,  Y10S977/762 ,  Y10S977/763 ,  Y10S977/811 ,  H01L2924/00014 ,  H01L2924/20651 ,  H01L2924/00 ,  H01L2924/01006

Abstract: Iridium oxide (IrOx) nanowires and a method forming the nanowires are provided. The method comprises: providing a growth promotion film with non-continuous surfaces, having a thickness in the range of 0.5 to 5 nanometers (nm), and made from a material such as Ti, Co, Ni, Au, Ta, polycrystalline silicon (poly-Si), SiGe, Pt, Ir, TiN, or TaN; establishing a substrate temperature in the range of 200 to 600 degrees C.; introducing oxygen as a precursor reaction gas; introducing a (methylcyclopentadienyl)(1,5-cyclooctadiene)iridium(I) precursor; using a metalorganic chemical vapor deposition (MOCVD) process, growing IrOx nanowires from the growth promotion film surfaces. The IrOx nanowires have a diameter in the range of 100 to 1000 Å, a length in the range of 1000 Å to 2 microns, an aspect ratio (length to width) of greater than 50:1. Further, the nanowires include single-crystal nanowire cores covered with an amorphous layer having a thickness of less than 10 Å.

Abstract translation: 提供氧化铱（IrOx）纳米线和形成纳米线的方法。 该方法包括：提供具有0.5至5纳米（nm）范围内的厚度的非连续表面的生长促进膜，并由诸如Ti，Co，Ni，Au，Ta，多晶硅 多晶硅），SiGe，Pt，Ir，TiN或TaN; 建立200〜600℃的基板温度。 引入氧气作为前体反应气体; 引入（甲基环戊二烯基）（1,5-环辛二烯）铱（I）前体; 使用金属有机化学气相沉积（MOCVD）工艺，从生长促进膜表面生长IrOx纳米线。 IrOx纳米线的直径在100至1000埃的范围内，长度在1000埃至2微米之间，纵横比（长宽比）大于50:1。 此外，纳米线包括覆盖有厚度小于Å的非晶层的单晶纳米线芯。

公开(公告)号：US07029924B2

公开(公告)日：2006-04-18

申请号：US10755654

申请日：2004-01-12

Applicant: Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei Pan ,  Wei-Wei Zhuang ,  David R. Evans ,  Masayuki Tajiri

Inventor： Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei Pan ,  Wei-Wei Zhuang ,  David R. Evans ,  Masayuki Tajiri

IPC: H01L21/00

CPC classification number: H01L27/101 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/51 ,  G11C2213/56 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147

Abstract: A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7-X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1-XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.

Abstract translation: 提供了一种用于形成缓冲层存储单元的方法。 该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）记忆膜; 形成存储器稳定的半导体缓冲层，通常为覆盖存储膜的金属氧化物; 并且形成覆盖半导体缓冲层的顶部电极。 在该方法的一些方面，半导体缓冲层由YBa 2 N 3 O 7-X（YBCO），氧化铟（In 2或2 O 3）或氧化钌（RuO 2 N 2），其厚度在10-200纳米（nm）的范围内。 顶部和底部电极可以是TiN / Ti，Pt / TiN / Ti，In / TiN / Ti，PtRhOx化合物或PtIrOx化合物。 CMR存储器膜可以是Pr 1-X C x MnO 3（PCMO）存储膜，其中x在0.1之间的区域 和0.6，厚度在10至200nm的范围内。

公开(公告)号：US20060068509A1

公开(公告)日：2006-03-30

申请号：US11262545

申请日：2005-10-28

Applicant: Sheng Hsu ,  Fengyan Zhang ,  Tingkai Li

Inventor： Sheng Hsu ,  Fengyan Zhang ,  Tingkai Li

IPC: H01L21/00

CPC classification number: H01L27/1159 ,  H01L21/84 ,  H01L27/11502 ,  H01L27/11585

Abstract: An MFIS memory array having a plurality of MFIS memory transistors with a word line connecting a plurality of MFIS memory transistor gates, wherein all MFIS memory transistors connected to a common word line have a common source, each transistor drain serves as a bit output, and all MFIS channels along a word line are separated by a P+ region and are further joined to a P+ substrate region on an SOI substrate by a P+ region is provided. Also provided are methods of making an MFIS memory array on an SOI substrate; methods of performing a block erase of one or more word lines, and methods of selectively programming a bit.

公开(公告)号：US07009231B2

公开(公告)日：2006-03-07

申请号：US11046620

申请日：2005-01-28

Applicant: Fengyan Zhang ,  Wei-Wei Zhuang ,  Jong-Jan Lee ,  Sheng Teng Hsu

Inventor： Fengyan Zhang ,  Wei-Wei Zhuang ,  Jong-Jan Lee ,  Sheng Teng Hsu

IPC: H01L29/94

CPC classification number: H01L21/31691 ,  H01L28/55 ,  H01L41/317

Abstract: A method for forming a doped PGO ferroelectric thin film, and related doped PGO thin film structures are described. The method comprising: forming either an electrically conductive or electrically insulating substrate; forming a doped PGO film overlying the substrate; annealing; crystallizing; and, forming a single-phase c-axis doped PGO thin film overlying the substrate, having a Curie temperature of greater than 200 degrees C. Forming a doped PGO film overlying the substrate includes depositing a doped precursor in the range between 0.1N and 0.5N, with a molecular formula of Pby-xMxGe3O11, where: M is a doping element; y=4.5 to 6; and, x=0.1 to 1. The element M can be Sn, Ba, Sr, Cd, Ca, Pr, Ho, La, Sb, Zr, or Sm.

Abstract translation: 描述了用于形成掺杂的PGO铁电薄膜的方法以及相关的掺杂PGO薄膜结构。 该方法包括：形成导电或电绝缘的衬底; 在衬底上形成掺杂的PGO膜; 退火; 结晶 并且形成覆盖在衬底上的单相c轴掺杂的PGO薄膜，其居里温度大于200℃。形成覆盖在衬底上的掺杂PGO膜包括在0.1N和0.5之间的范围内沉积掺杂的前体 N，具有分子式为Pb x Si x N x N x O 11，其中：M是掺杂物 元件; y = 4.5〜6; x = 0.1〜1。元素M可以是Sn，Ba，Sr，Cd，Ca，Pr，Ho，La，Sb，Zr或Sm。

公开(公告)号：US06998661B2

公开(公告)日：2006-02-14

申请号：US10385009

申请日：2003-03-10

Applicant: Fengyan Zhang ,  Jer-Shen Maa ,  Wei-Wei Zhuang ,  Sheng Teng Hsu

Inventor： Fengyan Zhang ,  Jer-Shen Maa ,  Wei-Wei Zhuang ,  Sheng Teng Hsu

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/1136 ,  H01L31/119

CPC classification number: H01L28/65 ,  C23C16/40 ,  H01L21/31691 ,  H01L28/55 ,  H01L28/56 ,  H01L28/60 ,  H01L28/75 ,  Y10T428/24917 ,  Y10T428/2495

Abstract: A method of forming an electrode and a ferroelectric thin film thereon, includes preparing a substrate; depositing an electrode on the substrate, wherein the electrode is formed of a material taken from the group of materials consisting of iridium and iridium composites; and forming a single-phase, c-axis PGO ferroelectric thin film thereon, wherein the ferroelectric thin film exhibits surface smoothness and uniform thickness. An integrated circuit includes a substrate; an electrode deposited on the substrate, wherein the electrode is formed of a material taken from the group of materials consisting of iridium and iridium composites, wherein the iridium composites are taken from the group of composites consisting of IrO2, Ir—Ta—O, Ir—Ti—O, Ir—Nb—O, Ir—Al—O, Ir—Hf—O, Ir—V—O, Ir—Zr—O and Ir—O; and a single-phase, c-axis PGO ferroelectric thin film formed on the electrode, wherein the ferroelectric thin film exhibits surface smoothness and uniform thickness.

Abstract translation: 一种在其上形成电极和铁电薄膜的方法，包括制备基板; 在所述基板上沉积电极，其中所述电极由从由铱和铱复合材料组成的材料组取得的材料形成; 并在其上形成单相c轴PGO铁电薄膜，其中铁电薄膜表现出平滑度和均匀的厚度。 集成电路包括基板; 沉积在所述基底上的电极，其中所述电极由从由铱和铱复合物组成的材料组中取得的材料形成，其中所述铱复合材料取自由IrO 2 ，Ir-Ta-O，Ir-Ti-O，Ir-Nb-O，Ir-Al-O，Ir-Hf-O，Ir-VO，Ir-Zr-O和Ir-O; 以及形成在电极上的单相c轴PGO铁电薄膜，其中铁电薄膜表现出平滑度和均匀的厚度。