SEMICONDUCTOR DEVICE INCLUDING FUSE
    72.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING FUSE 有权
    包括保险丝的半导体器件

    公开(公告)号:US20100193902A1

    公开(公告)日:2010-08-05

    申请号:US12502490

    申请日:2009-07-14

    IPC分类号: H01L23/525

    摘要: Provided is a semiconductor device including a fuse, in which a insulating layer surrounding the fuse or metal wiring is prevented from being damaged due to the cut of a fuse, which can occur when a repair process is performed. The semiconductor device includes a conductive line formed on a semiconductor layer, a protective layer formed on the conductive line, one or more fuses that are electrically connected to the conductive line, and a fuse protective layer formed on the one or more fuses, and spaced apart from the protective layer.

    摘要翻译: 提供了一种包括保险丝的半导体器件,其中防止在保险丝或金属布线周围的绝缘层由于保险丝的切断而被损坏,这在维修过程中可能发生。 半导体器件包括形成在半导体层上的导电线,形成在导电线上的保护层,与导电线电连接的一个或多个保险丝,以及形成在一个或多个保险丝上的保险丝保护层, 除了保护层。

    Methods of Forming Interlayer Dielectrics Having Air Gaps
    74.
    发明申请
    Methods of Forming Interlayer Dielectrics Having Air Gaps 有权
    形成具有空气间隙的层间电介质的方法

    公开(公告)号:US20090298282A1

    公开(公告)日:2009-12-03

    申请号:US12364598

    申请日:2009-02-03

    IPC分类号: H01L21/60

    摘要: Methods of forming an interlayer dielectric having an air gap are provided including forming a first insulating layer on a semiconductor substrate. The first insulating layer defines a trench. A metal wire is formed in the trench such that the metal wire is recessed beneath an upper surface of the first insulating layer. A metal layer is formed on the metal wire, wherein the metal layer includes a capping layer portion filling the recess, a upper portion formed on the capping layer portion, and an overhang portion formed on the portion of the first insulating layer adjacent to the trench protruding sideward from the upper portion. The first insulating layer is removed and a second insulating layer is formed on the semiconductor substrate to cover the metal layer, whereby an air gap is formed below the overhang portion of the metal layer. A portion of the second insulating layer is removed to expose the upper portion of the metal layer. The upper portion and the overhang portion of the metal layer are removed. A third insulating layer is formed on the semiconductor substrate from which the upper portion and the overhang portion have been removed to maintain the air gap.

    摘要翻译: 提供了形成具有气隙的层间电介质的方法,包括在半导体衬底上形成第一绝缘层。 第一绝缘层限定沟槽。 在沟槽中形成金属线,使得金属线在第一绝缘层的上表面下方凹入。 在金属线上形成金属层,其中金属层包括填充凹部的覆盖层部分,形成在覆盖层部分上的上部,和形成在与沟槽相邻的第一绝缘层的部分上的突出部分 从上部侧向突出。 去除第一绝缘层,并且在半导体衬底上形成覆盖金属层的第二绝缘层,由此在金属层的伸出部分的下方形成气隙。 去除第二绝缘层的一部分以露出金属层的上部。 去除金属层的上部和外伸部分。 在半导体基板上形成第三绝缘层,从该基板上去除上部和外伸部分以保持气隙。

    Methods of forming metal wiring layers for semiconductor devices
    76.
    发明申请
    Methods of forming metal wiring layers for semiconductor devices 审中-公开
    形成半导体器件的金属布线层的方法

    公开(公告)号:US20080070405A1

    公开(公告)日:2008-03-20

    申请号:US11800996

    申请日:2007-05-08

    IPC分类号: H01L21/44

    CPC分类号: H01L21/76843 H01L21/76856

    摘要: A method of forming a conductive plug for an integrated circuit device may include forming an insulating layer on an integrated circuit substrate with the insulating layer having a surface opposite the substrate and a recess therein. A titanium (Ti) layer may be formed on sidewalls of the recess and on the surface of the insulating layer opposite the substrate. After forming the titanium (Ti) layer, a reaction reducing layer may be formed on portions of the titanium layer on the surface of the insulating layer opposite the substrate by at least one of ionized physical vapour deposition (iPVD) and/or nitriding a portion of the titanium layer, and the reaction reducing layer may include a material other than titanium. After forming the reaction reducing layer, a TiN layer may be formed on the reaction reducing layer and on sidewalls of the recess in the insulating layer using metal organic chemical vapour deposition (MOCVD). After forming the TiN layer, a conductive plug may be formed on the TiN layer in the recess in the insulating layer.

    摘要翻译: 形成用于集成电路器件的导电插塞的方法可以包括在集成电路衬底上形成绝缘层,绝缘层具有与衬底相对的表面和凹槽。 钛(Ti)层可以形成在凹槽的侧壁上,并且在绝缘层的与衬底相对的表面上。 在形成钛(Ti)层之后,可以通过离子物理气相沉积(iPVD)和/或氮化一部分中的至少一种,在绝缘层的与基板相对的表面上的钛层的部分上形成反应还原层 的钛层,反应还原层可以包括钛以外的材料。 在形成反应还原层之后,可以使用金属有机化学气相沉积(MOCVD)在反应还原层上和在绝缘层的凹槽的侧壁上形成TiN层。 在形成TiN层之后,可以在绝缘层的凹部中的TiN层上形成导电塞。

    SUBSTRATE TREATMENT APPARATUS AND CLEANING METHOD
    78.
    发明申请
    SUBSTRATE TREATMENT APPARATUS AND CLEANING METHOD 审中-公开
    基板处理装置和清洁方法

    公开(公告)号:US20080041308A1

    公开(公告)日:2008-02-21

    申请号:US11830156

    申请日:2007-07-30

    IPC分类号: C23C16/00 B08B5/00

    摘要: A substrate treating apparatus and related cleaning method are disclosed. The apparatus includes a stage heater disposed in the reaction chamber, serving as a first electrode during the generation of in-situ plasma, and supporting a substrate, a shower head disposed in the reaction chamber opposing the stage heater, serving as a second electrode during the generation of the in-situ plasma, and supplying a reaction gas into the reaction chamber, a remote plasma generator disposed external to the reaction chamber and configured to supply a cleaning gas to the reaction chamber following activation of the cleaning gas, and a gas transmitter disposed between the reaction chamber and the remote plasma generator and configured to transmit the reaction gas and the cleaning gas to the shower head.

    摘要翻译: 公开了一种基板处理装置及其相关的清洁方法。 该装置包括设置在反应室中的级加热器,用于在原位等离子体生成期间作为第一电极,并且支撑基板,设置在与级加热器相对的反应室中的淋浴喷头,用作第二电极 产生原位等离子体,并将反应气体供应到反应室中;远程等离子体发生器,其设置在反应室外部并且构造成在清洁气体活化后向反应室供应清洁气体;气体 发射器设置在反应室和远程等离子体发生器之间,并被配置为将反应气体和清洁气体传输到淋浴头。