公开(公告)号：US20120219755A1

公开(公告)日：2012-08-30

申请号：US13407467

申请日：2012-02-28

Applicant: Young Cheol Bae ,  Seung-Hyun Lee

Inventor： Young Cheol Bae ,  Seung-Hyun Lee

IPC: B32B3/00 ,  G03F7/20 ,  G03F7/32

CPC classification number: G03F7/325 ,  G03F7/094 ,  G03F7/2041 ,  Y10T428/24355

Abstract: Provided are photoresist developer compositions that include a mixture of organic solvents. Also provided are methods of forming photolithographic patterns using negative tone development, coated substrates and electronic devices formed by the methods. The methods find particular applicability in the manufacture of electronic devices.

Abstract translation: 提供了包括有机溶剂的混合物的光致抗蚀剂显影剂组合物。 还提供了使用负色调显影，涂布基板和通过该方法形成的电子器件形成光刻图案的方法。 该方法在电子设备的制造中具有特别的适用性。

公开(公告)号：US20120217637A1

公开(公告)日：2012-08-30

申请号：US13465274

申请日：2012-05-07

Applicant: Woong Sun LEE ,  Qwan Ho CHUNG ,  Il Hwan CHO ,  Sang Joon LIM ,  Jong Woo YOO ,  Jin Ho BAE ,  Seung Hyun LEE

Inventor： Woong Sun LEE ,  Qwan Ho CHUNG ,  Il Hwan CHO ,  Sang Joon LIM ,  Jong Woo YOO ,  Jin Ho BAE ,  Seung Hyun LEE

IPC: H01L23/48

CPC classification number: H01L23/5384 ,  H01L23/5386 ,  H01L24/29 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29387 ,  H01L2224/2939 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83007 ,  H01L2224/83138 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The substrate for a semiconductor package includes a substrate body having a first surface and a second surface opposite to the first surface. Connection pads are formed near an edge of the first surface. Signal lines having conductive vias and first, second, and third line parts are formed. The first line parts are formed on the first surface and are connected to the connection pads and the conductive vias, which pass through the substrate body. The second line parts are formed on the first surface and connect to the conductive vias. The third line parts are formed on the second surface and connect to the conductive vias. The second and third line parts are formed to have substantially the same length. The semiconductor package utilizes the above substrate for processing data at a high speed.

Abstract translation: 用于半导体封装的衬底包括具有第一表面和与第一表面相对的第二表面的衬底本体。 在第一表面的边缘附近形成连接垫。 形成具有导电通孔和第一，第二和第三线部分的信号线。 第一线部分形成在第一表面上并且连接到穿过基板主体的连接焊盘和导电通孔。 第二线部分形成在第一表面上并连接到导电通孔。 第三线部分形成在第二表面上并连接到导电通孔。 第二和第三线部分形成为具有基本相同的长度。 半导体封装利用上述基板高速处理数据。

公开(公告)号：US20120189272A1

公开(公告)日：2012-07-26

申请号：US13388340

申请日：2010-06-14

Applicant: Hisayuki Kunigita ,  Seung-Hyun Lee ,  Taek-Joo Lee ,  Ju-Yeong Ji

Inventor： Hisayuki Kunigita ,  Seung-Hyun Lee ,  Taek-Joo Lee ,  Ju-Yeong Ji

IPC: H04N9/80

CPC classification number: H04N21/4788 ,  G06F3/147 ,  G06F2213/0038 ,  G09G5/363 ,  G09G2340/12 ,  G09G2370/16 ,  H04N21/4307 ,  H04N21/478

Abstract: A playback processing unit executes a playback process of content data. A control unit defines a display area for a communication tool to be executed, based on display instruction information that is defined in association with playback time information of the content data. The display processing unit uses a content image processed and played back and a text chat window of which a display area is defined, and generates an image for a display.

Abstract translation: 回放处理单元执行内容数据的回放处理。 控制单元基于与内容数据的重放时间信息相关联地定义的显示指示信息来定义要执行的通信工具的显示区域。 显示处理单元使用处理和回放的内容图像和定义了显示区域的文本聊天窗口，并且生成用于显示的图像。

公开(公告)号：US08223248B2

公开(公告)日：2012-07-17

申请号：US12491412

申请日：2009-06-25

Applicant: Seung Hyun Lee ,  Chan Ki Hwang ,  Seung Ho Lee ,  Hee Jin Park

Inventor： Seung Hyun Lee ,  Chan Ki Hwang ,  Seung Ho Lee ,  Hee Jin Park

IPC: H04N5/225 ,  H01L21/00 ,  H01L31/0232

CPC classification number: H01L27/14625 ,  H01L24/13 ,  H01L24/16 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14636 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13562 ,  H01L2224/1369 ,  H01L2224/1379 ,  H01L2224/138 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: An image sensor module is presented which includes a semiconductor chip, a holder and a coupling member. The semiconductor chip has a semiconductor chip body; an image sensing section over the semiconductor chip body; and bonding pads on the semiconductor chip body. The holder is mounted over the semiconductor chip and has an insulation section over the semiconductor chip body; connection patterns on the insulation section which are electrically coupled to the bonding pads; and a transparent cover over the image sensing section which is connected to the insulation section. The coupling member is interposed between the holder and the semiconductor chip for coupling together the holder to the semiconductor chip.

Abstract translation: 提出了一种图像传感器模块，其包括半导体芯片，保持器和联接构件。 半导体芯片具有半导体芯片体; 半导体芯片本体上的图像感测部分; 以及半导体芯片主体上的接合焊盘。 保持器安装在半导体芯片上，并且在半导体芯片主体上方具有绝缘部分; 绝缘部分上的连接图案，其电耦合到接合焊盘; 以及连接到绝缘部分的图像感测部分上方的透明盖。 联接构件插入在保持器和半导体芯片之间，用于将保持器联接在半导体芯片上。

公开(公告)号：US08222083B2

公开(公告)日：2012-07-17

申请号：US12758973

申请日：2010-04-13

Applicant: Seung Hyun Lee ,  Seung Taek Yang

Inventor： Seung Hyun Lee ,  Seung Taek Yang

IPC: H01L21/304 ,  H01L21/50

CPC classification number: H01L24/10 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05553 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16105 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  Y10S438/977 ,  H01L2924/00

Abstract: A semiconductor package includes a semiconductor chip provided with a first surface having a bonding pad, a second surface opposing to the first surface and side surfaces; a first redistribution pattern connected with the bonding pad and extending along the first surface from the bonding pad to an end portion of the side surface which meets with the second surface; and a second redistribution pattern disposed over the first redistribution pattern and extending from the side surfaces to the first surface. In an embodiment of the present invention, in which the first redistribution pattern connected with the bonding pad is formed over the semiconductor chip and the second redistribution pattern is formed over the first redistribution pattern, it is capable of reducing a length for signal transfer since the second redistribution pattern is used as an external connection terminal. It is also capable of processing data with high speed, as well as protecting the semiconductor chip having weak brittleness, since the semiconductor package is connected to the substrate without a separate solder ball.

Abstract translation: 半导体封装包括设置有具有接合焊盘的第一表面的半导体芯片，与第一表面相对的第二表面和侧表面; 与所述接合焊盘连接并沿着所述第一表面从所述接合焊盘延伸到与所述第二表面相交的所述侧表面的端部的第一再分布图案; 以及设置在所述第一再分布图案上并且从所述侧表面延伸到所述第一表面的第二再分配图案。 在本发明的一个实施例中，其中与焊盘连接的第一再分布图案形成在半导体芯片之上，并且第二再分配图案形成在第一再分配图案之上，其能够减小用于信号传输的长度，因为 第二再分配模式用作外部连接终端。 由于半导体封装没有单独的焊球而连接到衬底，所以它也能够高速处理数据以及保护具有弱脆性的半导体芯片。

公开(公告)号：US20120171617A1

公开(公告)日：2012-07-05

申请号：US13341935

申请日：2011-12-31

Applicant: Young Cheol BAE ,  Thomas H. Peterson ,  Yi Liu ,  Jong Keun Park ,  Seung-Hyun Lee ,  Thomas Cardolaccia

Inventor： Young Cheol BAE ,  Thomas H. Peterson ,  Yi Liu ,  Jong Keun Park ,  Seung-Hyun Lee ,  Thomas Cardolaccia

IPC: G03F7/20 ,  G03F7/004 ,  C08F224/00

CPC classification number: G03F7/0397 ,  C08F220/28 ,  G03F7/11 ,  G03F7/2041 ,  G03F7/322 ,  G03F7/325

Abstract: Provided are polymers that include a unit comprising a particular acetal moiety and a unit comprising a lactone moiety. Also provided are photoresist compositions containing such a polymer, substrates coated with the photoresist compositions and methods of forming photolithographic patterns. The polymers, compositions, methods and coated substrates find particular applicability in the manufacture of semiconductor devices.

Abstract translation: 提供的是包括包含特定缩醛部分的单元和包含内酯部分的单元的聚合物。 还提供含有这种聚合物的光致抗蚀剂组合物，用光致抗蚀剂组合物涂覆的基材和形成光刻图案的方法。 聚合物，组合物，方法和涂覆的基底在半导体器件的制造中具有特别的适用性。

公开(公告)号：US20120040709A1

公开(公告)日：2012-02-16

申请号：US13264756

申请日：2010-04-02

Applicant: Kuk Jin Song ,  Seung Hyun Lee

Inventor： Kuk Jin Song ,  Seung Hyun Lee

IPC: H04W52/04

CPC classification number: H04W52/262 ,  H04W52/365

Abstract: Disclosed is an apparatus for reporting transmission power. The apparatus for reporting transmission power includes a transmission power normalization unit, a message generation unit, and a transmission unit. The transmission power normalization unit normalizes a first transmission power at a current Modulation and Coding Scheme (MCS) level into a second transmission power at a reference MCS level, the current MCS level being an MCS level of a burst which is intended to comprise a transmission power report of a terminal. The message generation unit generates a message comprising the transmission power report of the terminal with the second transmission power defined therein. The transmission unit transmits the generated message to a base station.

Abstract translation: 公开了一种报告发送功率的装置。 用于报告发送功率的装置包括发送功率归一化单元，消息生成单元和发送单元。 传输功率归一化单元将当前调制和编码方案（MCS）级别的第一传输功率归一化为参考MCS级别的第二传输功率，当前MCS级别是旨在包括传输的突发的MCS级别 终端电力报告。 消息生成单元生成包含终端的发送功率报告和消息中定义的第二发送功率的消息。 发送单元将生成的消息发送到基站。

公开(公告)号：US20120009736A1

公开(公告)日：2012-01-12

申请号：US13241812

申请日：2011-09-23

Applicant: Seung Taek YANG ,  Min Suk SUH ,  Seung Hyun LEE ,  Jong Hoon KIM

Inventor： Seung Taek YANG ,  Min Suk SUH ,  Seung Hyun LEE ,  Jong Hoon KIM

IPC: H01L21/603

CPC classification number: H01L23/481 ,  H01L23/3128 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05099

Abstract: A stacked semiconductor package and a method for manufacturing the same are presented which exhibit a reduced electrical resistance and an increased junction force. The semiconductor package includes at least two semiconductor chips stacked upon each other. Each semiconductor chip has a plurality of bonding pads formed on upper surfaces and has via-holes. First wiring lines are located on the upper surfaces of the semiconductor chips, on the surfaces of the via-holes, and respectively connected onto their respective bonding pads. Second wiring lines are located on lower surfaces of the semiconductor chips and on the surfaces of the respective via-holes which connect to their respective first wiring lines. The semiconductor chips are stacked so that the first wiring lines on an upper surface of an upwardly positioned semiconductor chip are respectively joined with corresponding second wiring lines formed on a lower surface of a downwardly positioned semiconductor chip.

Abstract translation: 本发明提供一种叠层半导体封装及其制造方法，其具有降低的电阻和增加的接合力。 半导体封装包括彼此堆叠的至少两个半导体芯片。 每个半导体芯片具有形成在上表面上并具有通孔的多个接合焊盘。 第一布线位于半导体芯片的上表面上，位于通孔的表面上，分别连接到它们各自的焊盘上。 第二布线位于半导体芯片的下表面和连接到它们各自的第一布线的相应通孔的表面上。 半导体芯片被堆叠，使得位于向上定位的半导体芯片的上表面上的第一布线分别与形成在向下定位的半导体芯片的下表面上的对应的第二布线接合。

公开(公告)号：US07795139B2

公开(公告)日：2010-09-14

申请号：US11777388

申请日：2007-07-13

Applicant: Kwon Whan Han ,  Chang Jun Park ,  Min Suk Suh ,  Seong Cheol Kim ,  Sung Min Kim ,  Seung Taek Yang ,  Seung Hyun Lee ,  Jong Hoon Kim ,  Ha Na Lee

Inventor： Kwon Whan Han ,  Chang Jun Park ,  Min Suk Suh ,  Seong Cheol Kim ,  Sung Min Kim ,  Seung Taek Yang ,  Seung Hyun Lee ,  Jong Hoon Kim ,  Ha Na Lee

IPC: H01L21/4763

CPC classification number: H01L21/76898 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16145 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/013

Abstract: A method for manufacturing a semiconductor package includes forming a groove in the portion outside of the bonding pad of a semiconductor chip provided with the bonding pad on an upper surface thereof; forming an insulation layer on the side wall of the groove; forming a metal layer over the semiconductor chip so as to fill the groove formed with the insulation layer; etching the metal layer to simultaneously form a through silicon via for filling the groove and a distribution layer for connecting the through silicon via and the bonding pad; and removing a rear surface of the semiconductor chip such that the lower surface of the through silicon via protrudes from the semiconductor chip.

Abstract translation: 一种半导体封装的制造方法，其特征在于，在设置有所述接合焊盘的半导体芯片的焊盘的外侧的部分的外表面形成有槽， 在所述槽的侧壁上形成绝缘层; 在半导体芯片上形成金属层，以填充形成有绝缘层的槽; 蚀刻金属层以同时形成用于填充槽的通过硅通孔和用于连接通过硅通孔和接合焊盘的分布层; 以及去除所述半导体芯片的后表面，使得所述贯穿硅通孔的下表面从所述半导体芯片突出。

公开(公告)号：US20100197077A1

公开(公告)日：2010-08-05

申请号：US12758973

申请日：2010-04-13

Applicant: Seung Hyun LEE ,  Seung Taek YANG

Inventor： Seung Hyun LEE ,  Seung Taek YANG

IPC: H01L21/50

CPC classification number: H01L24/10 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05553 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16105 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  Y10S438/977 ,  H01L2924/00

Abstract: A semiconductor package includes a semiconductor chip provided with a first surface having a bonding pad, a second surface opposing to the first surface and side surfaces; a first redistribution pattern connected with the bonding pad and extending along the first surface from the bonding pad to an end portion of the side surface which meets with the second surface; and a second redistribution pattern disposed over the first redistribution pattern and extending from the side surfaces to the to first surface. In an embodiment of the present invention, in which the first redistribution pattern connected with the bonding pad is formed over the semiconductor chip and the second redistribution pattern is formed over the first redistribution pattern, it is capable of reducing a length for signal transfer since the second redistribution pattern is used as an external connection terminal. It is also capable of processing data with high speed, as well as protecting the semiconductor chip having weak brittleness, since the semiconductor package is connected to the substrate without a separate solder ball.

Abstract translation: 半导体封装包括设置有具有接合焊盘的第一表面的半导体芯片，与第一表面相对的第二表面和侧表面; 与所述接合焊盘连接并沿着所述第一表面从所述接合焊盘延伸到与所述第二表面相交的所述侧表面的端部的第一再分布图案; 以及第二再分配图案，其设置在所述第一再分布图案上并且从所述侧表面延伸到所述第一表面。 在本发明的一个实施例中，其中与焊盘连接的第一再分布图案形成在半导体芯片之上，并且第二再分配图案形成在第一再分配图案之上，其能够减小用于信号传输的长度，因为 第二再分配模式用作外部连接终端。 由于半导体封装没有单独的焊球而连接到衬底，所以它也能够高速处理数据以及保护具有弱脆性的半导体芯片。