公开(公告)号：US07368821B2

公开(公告)日：2008-05-06

申请号：US11231751

申请日：2005-09-22

申请人： Sang-Young Kim ,  Jin-Ho Kim ,  Hee-Jin Park ,  Young-Hee Song ,  Tae-Sung Yoon

发明人： Sang-Young Kim ,  Jin-Ho Kim ,  Hee-Jin Park ,  Young-Hee Song ,  Tae-Sung Yoon

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/49816 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/303 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/094 ,  H05K2201/09781 ,  H05K2201/10734 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In example embodiments of the present invention, a structure of a BGA semiconductor chip package includes a substrate having first and second surfaces, a semiconductor chip having a plurality of bonding pads, and mounted on the first surface of the substrate, and plurality of in/out (I/O) solder balls and dummy solder balls provided on the second surface of the substrate, wherein the I/O solder balls are electrically connected to the semiconductor chip and the dummy solder balls are electrically isolated from the semiconductor chip, and the I/O solder balls and the dummy solder balls have the same ball size and ball pitch and are uniformly provided over the second surface of the substrate.

摘要翻译： 在本发明的示例性实施例中，BGA半导体芯片封装的结构包括具有第一和第二表面的衬底，具有多个焊盘的半导体芯片，并且安装在衬底的第一表面上，以及多个入/ （I / O）焊球和设置在基板的第二表面上的虚拟焊球，其中I / O焊球电连接到半导体芯片，并且虚拟焊球与半导体芯片电隔离，并且 I / O焊球和虚拟焊球具有相同的球尺寸和球间距，并均匀地设置在基板的第二表面上。

公开(公告)号：US08321153B2

公开(公告)日：2012-11-27

申请号：US12526607

申请日：2007-12-28

申请人： Kun Soo Park ,  Joo Young Yoon ,  Sun Ho Lee ,  Eun Ok Paek ,  Hee Jin Park ,  Sang Won Lee

发明人： Kun Soo Park ,  Joo Young Yoon ,  Sun Ho Lee ,  Eun Ok Paek ,  Hee Jin Park ,  Sang Won Lee

IPC分类号： G01N33/48 ,  G01N33/50 ,  G01N31/00 ,  C12Q1/00

CPC分类号： H01J49/0036

摘要： Disclosed herein is a method of finding an isotopic cluster in a polypeptide and determining the monoisotopic mass of the cluster. The method comprises an algorithm for finding an isotopic cluster based on a probabilistic model, defined by each of peaks in the isotopic cluster, and determining the monoisotopic mass of the isotopic cluster. The probabilistic model of the isotopic cluster includes characteristic functions for mass, that is, a function of the ratio of two peak intensities, and a function of the product of two ratios obtained from three peaks. These characteristic functions for mass define the shape of peaks acceptable in an actual isotopic cluster for the mass of any isotopic cluster. The algorithm of finding the isotopic cluster based on the functions uses the characteristics to score the degree of the approximation of any isotopic cluster to the spectral shape of a theoretical cluster.

摘要翻译： 本文公开了一种在多肽中发现同位素簇并确定簇的单同位素质量的方法。 该方法包括基于由同位素簇中的每个峰定义的概率模型以及确定同位素簇的单同位素质量来找到同位素簇的算法。 同位素簇的概率模型包括质量的特征函数，即两个峰值强度的比值的函数，以及从三个峰值得到的两个比值的乘积的函数。 质量的这些特征函数定义了任何同位素簇的质量在实际同位素簇中可接受的峰的形状。 基于该函数找到同位素簇的算法使用特征来将任何同位素簇的近似程度评估为理论簇的光谱形状。

公开(公告)号：US20120113181A1

公开(公告)日：2012-05-10

申请号：US13317853

申请日：2011-10-31

申请人： Ji Han Kwon ,  Ju Hwan Yang ,  Jun Young Kim ,  Ha Yoon Song ,  Jae Hun Kim ,  Hee Jin Park ,  Young Seuck Yoo ,  Sung Nam Cho

发明人： Ji Han Kwon ,  Ju Hwan Yang ,  Jun Young Kim ,  Ha Yoon Song ,  Jae Hun Kim ,  Hee Jin Park ,  Young Seuck Yoo ,  Sung Nam Cho

IPC分类号： B41J29/38

CPC分类号： H05K3/0079 ,  H05K3/0008 ,  H05K3/244 ,  H05K3/28 ,  H05K2203/013 ,  H05K2203/166

摘要： There is provided a resist ink printing device according to an exemplary embodiment of the present invention including: a transfer unit transferring a substrate on which lead-in wires for electrolytic gold plating are patterned into a main body; a controller formed on the main body to measure a warpage degree of the substrate and recognizing a gerber file stored with circuit diagram information of the substrate to compensate for the warpage degree of the substrate and correct the gerber file; and at least one inkjet printing head part discharging liquid photo resist ink to the lead-in wires by the corrected gerber file.

摘要翻译： 提供了根据本发明的示例性实施例的抗蚀剂油墨打印装置，包括：转印单元，其将用于电解镀金的引入线的图案化的基板转印到主体中; 形成在所述主体上的控制器，用于测量所述基板的翘曲度，并且识别与所述基板的电路图信息一起存储的格氏文件，以补偿所述基板的翘曲程度并校正所述格子文件; 以及至少一个喷墨打印头部分，其通过校正的gerber文件将液体光致抗蚀剂油墨喷射到引入线。

公开(公告)号：US20100259657A1

公开(公告)日：2010-10-14

申请号：US12491412

申请日：2009-06-25

申请人： Seung Hyun LEE ,  Chan Ki HWANG ,  Seung Ho LEE ,  Hee Jin PARK

发明人： Seung Hyun LEE ,  Chan Ki HWANG ,  Seung Ho LEE ,  Hee Jin PARK

IPC分类号： H04N5/335

CPC分类号： H01L27/14625 ,  H01L24/13 ,  H01L24/16 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14636 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13562 ,  H01L2224/1369 ,  H01L2224/1379 ,  H01L2224/138 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： An image sensor module is presented which includes a semiconductor chip, a holder and a coupling member. The semiconductor chip has a semiconductor chip body; an image sensing section over the semiconductor chip body; and bonding pads on the semiconductor chip body. The holder is mounted over the semiconductor chip and has an insulation section over the semiconductor chip body; connection patterns on the insulation section which are electrically coupled to the bonding pads; and a transparent cover over the image sensing section which is connected to the insulation section. The coupling member is interposed between the holder and the semiconductor chip for coupling together the holder to the semiconductor chip.

摘要翻译： 提出了一种图像传感器模块，其包括半导体芯片，保持器和联接构件。 半导体芯片具有半导体芯片体; 半导体芯片本体上的图像感测部分; 以及半导体芯片主体上的接合焊盘。 保持器安装在半导体芯片上，并且在半导体芯片主体上方具有绝缘部分; 绝缘部分上的连接图案，其电耦合到接合焊盘; 以及连接到绝缘部分的图像感测部分上方的透明盖。 联接构件插入在保持器和半导体芯片之间，用于将保持器联接在半导体芯片上。

公开(公告)号：US07485959B2

公开(公告)日：2009-02-03

申请号：US11330773

申请日：2006-01-11

申请人： Cheol-Joon Yoo ,  Jin-Ho Kim ,  Hee-Jin Park ,  Tae-Sung Yoon ,  Chan-Suk Lee

发明人： Cheol-Joon Yoo ,  Jin-Ho Kim ,  Hee-Jin Park ,  Tae-Sung Yoon ,  Chan-Suk Lee

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H05K3/3436 ,  H01L23/3128 ,  H01L24/10 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/48091 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2201/10977 ,  H05K2203/0568 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and a package mounting substrate can be joined using a conductive material column. Each of the semiconductor package and the package mounting substrate include an insulating protective opening exposing a wiring layer therein. The solder column resides within the insulating protective openings to electrically couple the wiring layers. The insulating protective openings protect the solder column against stress faults to form reliable electrical connections and to support high-density electrical connections between the semiconductor package and the package mounting substrate.

摘要翻译： 半导体封装和封装安装基板可以使用导电材料柱接合。 半导体封装和封装安装衬底中的每一个包括暴露其中的布线层的绝缘保护开口。 焊料柱位于绝缘保护开口内，以电连接布线层。 绝缘保护开口保护焊料柱免受应力故障的影响，形成可靠的电连接并支持半导体封装和封装安装基板之间的高密度电连接。

公开(公告)号：US20060231952A1

公开(公告)日：2006-10-19

申请号：US11231751

申请日：2005-09-22

申请人： Sang-Young Kim ,  Jin-Ho Kim ,  Hee-Jin Park ,  Young-Hee Song ,  Tae-Sung Yoon

发明人： Sang-Young Kim ,  Jin-Ho Kim ,  Hee-Jin Park ,  Young-Hee Song ,  Tae-Sung Yoon

IPC分类号： H01L23/48

CPC分类号： H01L23/49816 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/303 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/094 ,  H05K2201/09781 ,  H05K2201/10734 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In example embodiments of the present invention, a structure of a BGA semiconductor chip package includes a substrate having first and second surfaces, a semiconductor chip having a plurality of bonding pads, and mounted on the first surface of the substrate, and plurality of in/out (I/O) solder balls and dummy solder balls provided on the second surface of the substrate, wherein the I/O solder balls are electrically connected to the semiconductor chip and the dummy solder balls are electrically isolated from the semiconductor chip, and the I/O solder balls and the dummy solder balls have the same ball size and ball pitch and are uniformly provided over the second surface of the substrate.

摘要翻译： 在本发明的示例性实施例中，BGA半导体芯片封装的结构包括具有第一和第二表面的衬底，具有多个焊盘的半导体芯片，并且安装在衬底的第一表面上，以及多个入/ （I / O）焊球和设置在基板的第二表面上的虚拟焊球，其中I / O焊球电连接到半导体芯片，并且虚拟焊球与半导体芯片电隔离，并且 I / O焊球和虚拟焊球具有相同的球尺寸和球间距，并均匀地设置在基板的第二表面上。

公开(公告)号：US07629679B2

公开(公告)日：2009-12-08

申请号：US11286314

申请日：2005-11-23

申请人： Hee-Jin Park

发明人： Hee-Jin Park

IPC分类号： H01L23/02

CPC分类号： G06K19/07724 ,  H01L21/565 ,  H01L23/3121 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/12041 ,  H01L2924/181 ,  H05K1/117 ,  H05K3/284 ,  H05K2201/0989 ,  H05K2203/1316 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes a printed circuit board, a semiconductor chip mounted on the printed circuit board, a wire structured to electrically connect the printed circuit board to the semiconductor chip, and an encapsulant that protects the semiconductor chip and the wire, the encapsulant disposed on the printed circuit board such that the encapsulant covers a surface of the printed in an edge region of the printed circuit board and exposes another surface of the printed circuit board in another edge region of the printed circuit board.

摘要翻译： 半导体封装包括印刷电路板，安装在印刷电路板上的半导体芯片，将印刷电路板电连接到半导体芯片的导线以及保护半导体芯片和导线的密封剂，密封剂设置在 印刷电路板，使得密封剂覆盖印刷电路板的边缘区域中的印刷表面，并将印刷电路板的另一个表面暴露在印刷电路板的另一个边缘区域中。

公开(公告)号：US07374079B2

公开(公告)日：2008-05-20

申请号：US10872444

申请日：2004-06-22

申请人： Deok-Young Nam ,  Hyung-Seok Kim ,  Jun-Hyung Kim ,  Hee-Jin Park

发明人： Deok-Young Nam ,  Hyung-Seok Kim ,  Jun-Hyung Kim ,  Hee-Jin Park

IPC分类号： G06K19/06

CPC分类号： G07F7/1008 ,  G06Q20/04 ,  G06Q20/10 ,  G06Q20/102 ,  G06Q20/105 ,  G06Q20/32 ,  G06Q20/3223 ,  G06Q20/341 ,  G06Q40/00 ,  G06Q40/02 ,  G07F7/0886

摘要： A method of providing banking services by use of a mobile communication system having a removable built-in integrated circuit (IC) card chip in which personal identification number (PIN) information and related information on financial accounts of a user are stored. The method includes selecting an electronic bankbook service and selecting any one from financial transactions for the electronic bankbook service and comparing the PIN information input at the mobile communication system with the PIN information stored in the IC card chip, and authenticating access to data stored in the IC card chip on the mobile communication system. The method further includes displaying financial account information of the user stored in the IC card chip in a display window of the mobile communication system and forming a financial transaction request message using the related information of the selected financial account through a banking application built in the mobile communication system, and transmitting the financial transaction request message to the banking server. The method further includes performing a predetermined customer authentication process with respect to the financial transactions and financial accounts at the banking server, and transmitting a financial transaction response message to the mobile communication system and displaying the resulting transaction history in the display window of the mobile communication system.

摘要翻译： 一种通过使用移动通信系统提供银行服务的方法，所述移动通信系统具有存储个人识别码（PIN）信息和用户的财务账户的相关信息的可拆卸的内置集成电路（IC）卡芯片。 该方法包括：从电子银行业务的金融交易中选择一个电子银行存折服务并选择任何一个，并将移动通信系统输入的PIN信息与存储在IC卡芯片中的PIN信息进行比较，以及对存储在IC卡芯片中的数据进行认证访问 IC卡芯片在移动通信系统上。 该方法还包括在移动通信系统的显示窗口中显示存储在IC卡芯片中的用户的财务帐户信息，并通过内置在移动通信系统中的银行应用程序，使用所选金融账户的相关信息形成金融交易请求消息 通信系统，并向金融服务器发送金融交易请求消息。 该方法还包括对银行服务器上的金融交易和金融账户执行预定的客户认证处理，并向移动通信系统发送金融交易响应消息，并将所得交易历史显示在移动通信的显示窗口中 系统。

公开(公告)号：US20060157848A1

公开(公告)日：2006-07-20

申请号：US11330773

申请日：2006-01-11

申请人： Cheol-Joon Yoo ,  Jin-Ho Kim ,  Hee-Jin Park ,  Tae-Sung Yoon ,  Chan-Suk Lee

发明人： Cheol-Joon Yoo ,  Jin-Ho Kim ,  Hee-Jin Park ,  Tae-Sung Yoon ,  Chan-Suk Lee

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H05K3/3436 ,  H01L23/3128 ,  H01L24/10 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/48091 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2201/10977 ,  H05K2203/0568 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In one embodiment, a semiconductor package and a package mounting substrate are joined using a conductive material column such as a solder column. Each of the semiconductor package and the package mounting substrate include an insulating protective opening exposing a wiring layer therein. The solder column resides within the insulating protective openings to electrically couple the wiring layers. By forming the insulating protective openings with sufficient depth, each protects the solder column against stress faults and thereby forms more reliable electrical connections and supports high-density electrical connections between the semiconductor package and the package mounting substrate.

摘要翻译： 在一个实施例中，使用诸如焊料柱的导电材料柱将半导体封装和封装安装基板接合。 半导体封装和封装安装衬底中的每一个包括暴露其中的布线层的绝缘保护开口。 焊料柱位于绝缘保护开口内，以电连接布线层。 通过形成具有足够深度的绝缘保护开口，每个保护焊料柱免受应力故障，从而形成更可靠的电连接并且支持半导体封装和封装安装基板之间的高密度电连接。

公开(公告)号：US06857470B2

公开(公告)日：2005-02-22

申请号：US10719670

申请日：2003-11-20

申请人： Hee-Jin Park ,  Tae-Gyeong Chung ,  Eun-Chul Ahn

发明人： Hee-Jin Park ,  Tae-Gyeong Chung ,  Eun-Chul Ahn

IPC分类号： H01L23/34 ,  H01L23/31 ,  H01L23/36 ,  H01L25/065 ,  H01L21/50 ,  F28F7/00

CPC分类号： H01L24/06 ,  H01L23/3128 ,  H01L23/36 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/32057 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48479 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/4943 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2225/0651 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/48471 ,  H01L2224/45099 ,  H01L2224/4554

摘要： The present invention provides a stacked chip package having at least one heat transfer wire. The heat transfer wire is disposed between the stacked chips and at least one end of each transfer wire is connected to a dummy pad provided on the board. Therefore, the heat generated by the chips and trapped between the chips can be effectively dissipated. The heat transfer wires can be formed on the uppermost chip of the stacked chips to enhance the heat dissipation. In addition, by controlling the number or the size of the heat transfer wire, the thermal characteristics of the stacked chip package can be modified.

摘要翻译： 本发明提供一种具有至少一个传热线的堆叠式芯片封装。 传热线设置在堆叠的芯片之间，并且每个传输线的至少一端连接到设置在板上的虚拟焊盘。 因此，可以有效地消散由芯片产生的并被捕获在芯片之间的热量。 传热线可以形成在堆叠芯片的最上面的芯片上，以增强散热。 此外，通过控制传热丝的数量或尺寸，可以改变堆叠的芯片封装的热特性。