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    IMAGE SENSOR MONITOR STRUCTURE IN SCRIBE AREA
    71.
    发明申请
    IMAGE SENSOR MONITOR STRUCTURE IN SCRIBE AREA 失效
    图像传感器监控结构在SCRIBE区域

    公开(公告)号：US20090237103A1

    公开(公告)日：2009-09-24

    申请号：US12051868

    申请日：2008-03-20

    Applicant: John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Sambasivan Narayan ,  Anthony J. Perri ,  Richard J. Rassel ,  Tian Xia

    Inventor： John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Sambasivan Narayan ,  Anthony J. Perri ,  Richard J. Rassel ,  Tian Xia

    IPC: G01R31/26 ,  H01L23/00 ,  G06F17/50

    CPC classification number: H01L22/34 ,  G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor die including a semiconductor chip and a test structure, located in a scribe area, is designed and manufactured. The test structure includes an array of complementary metal oxide semiconductor (CMOS) image sensors that are of the same type as CMOS image sensors employed in another array in the semiconductor chip and having a larger array size. Such a test structure is provided in a design phase by providing a design structure in which the orientations of the CMOS image sensors match between the two arrays. The test structure provides effective and accurate monitoring of manufacturing processes through in-line testing before a final test on the semiconductor chip.

    Abstract translation: 设计并制造了包括位于划线区域中的半导体芯片和测试结构的半导体管芯。 测试结构包括互补金属氧化物半导体（CMOS）图像传感器的阵列，其与在半导体芯片中的另一阵列中使用并具有较大阵列尺寸的CMOS图像传感器具有相同的类型。 通过提供CMOS图像传感器的取向在两个阵列之间匹配的设计结构，在设计阶段提供了这种测试结构。 测试结构通过在半导体芯片上的最终测试之前的在线测试来提供对制造工艺的有效和准确的监控。

    Multi-orientation semiconductor-on-insulator (SOI) substrate, and method of fabricating same
    72.
    发明授权
    Multi-orientation semiconductor-on-insulator (SOI) substrate, and method of fabricating same 有权
    多取向半导体绝缘体（SOI）基板及其制造方法

    公开(公告)号：US07531392B2

    公开(公告)日：2009-05-12

    申请号：US11276366

    申请日：2006-02-27

    Applicant: John J. Ellis-Monaghan ,  Mark D. Jaffe

    Inventor： John J. Ellis-Monaghan ,  Mark D. Jaffe

    IPC: H01L21/84

    CPC classification number: H01L21/84 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/76264 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/045

    Abstract: The present invention relates to semiconductor-on-insulator (SOI) substrate structures that contain surface semiconductor regions of different crystal orientations located directly on an insulator layer. The present invention also relates to methods for fabricating such SOI substrate structures, by growing an insulator layer directly on a multi-orientation bulk semiconductor substrate that comprises surface semiconductor regions of different crystal orientations located directly on a semiconductor base layer, and removing the semiconductor base layer, thereby forming a multi-orientation SOI substrate structure that comprises surface semiconductor regions of different crystal orientations located directly on the insulator layer.

    Abstract translation: 本发明涉及绝缘体上半导体（SOI）衬底结构，其包含直接位于绝缘体层上的不同晶体取向的表面半导体区域。 本发明还涉及制造这种SOI衬底结构的方法，通过直接在多取向体半导体衬底上生长绝缘体层，该绝缘体层包括直接位于半导体基底层上的不同晶体取向的表面半导体区域，以及去除半导体基底 从而形成包括直接位于绝缘体层上的不同晶体取向的表面半导体区域的多取向SOI衬底结构。

    IMAGE SENSOR INCLUDING SPATIALLY DIFFERENT ACTIVE AND DARK PIXEL INTERCONNECT PATTERNS
    74.
    发明申请
    IMAGE SENSOR INCLUDING SPATIALLY DIFFERENT ACTIVE AND DARK PIXEL INTERCONNECT PATTERNS 有权
    图像传感器包括空间不同的主动和深色像素互连图案

    公开(公告)号：US20080111159A1

    公开(公告)日：2008-05-15

    申请号：US11560019

    申请日：2006-11-15

    Applicant: Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel

    Inventor： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel

    IPC: H01L31/101 ,  H01L29/765 ,  H01L23/52 ,  H01L21/339

    CPC classification number: H01L27/14636 ,  H01L27/14603 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14645 ,  H01L27/14687

    Abstract: An interconnect layout, an image sensor including the interconnect layout and a method for fabricating the image sensor each use a first electrically active physical interconnect layout pattern within an active pixel region and a second electrically active physical interconnect layout pattern spatially different than the first electrically active physical interconnect layout pattern within a dark pixel region. The second electrically active physical interconnect layout pattern includes at least one electrically active interconnect layer interposed between a light shield layer and a photosensor region aligned therebeneath, thus generally providing a higher wiring density. The higher wiring density within the second layout pattern provides that that the image sensor may be fabricated with enhanced manufacturing efficiency and a reduction of metallization levels.

    Abstract translation: 互连布局，包括互连布局的图像传感器和用于制造图像传感器的方法各自使用有源像素区域内的第一电活性物理互连布局图案和在空间上不同于第一电活动的第二电活动物理互连布局图案 物理互连布局图案在暗像素区域内。 第二电活动物理互连布局图案包括插入在遮光层和在其下对准的光电传感器区域之间的至少一个电活动互连层，因此通常提供更高的布线密度。 在第二布局图案中更高的布线密度提供了图像传感器可以制造成具有增强的制造效率和金属化水平的降低。

    Pixel sensor having doped isolation structure sidewall
    75.
    发明授权
    Pixel sensor having doped isolation structure sidewall 有权
    具有掺杂隔离结构侧壁的像素传感器

    公开(公告)号：US07141836B1

    公开(公告)日：2006-11-28

    申请号：US10908885

    申请日：2005-05-31

    Applicant: James W. Adkisson ,  Mark D. Jaffe ,  Robert K. Leidy

    Inventor： James W. Adkisson ,  Mark D. Jaffe ,  Robert K. Leidy

    IPC: H01L27/148

    CPC classification number: H01L27/14603 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14683

    Abstract: A novel pixel sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. An isolation structure is formed adjacent to the photosensitive device pinning layer. The isolation structure includes a dopant region comprising material of the first conductivity type selectively formed along a sidewall of the isolation structure that is adapted to electrically couple the surface pinning layer to the underlying substrate. The corresponding method for forming the dopant region selectively formed along the sidewall of the isolation structure comprises an out-diffusion process whereby dopant materials present in a doped material layer formed along selected portions in the isolation structure are driven into the underlying substrate during an anneal. Alternately, or in conjunction, an angled ion implantation of dopant material in the isolation structure sidewall may be performed by first fabricating a photoresist layer and reducing its size by removing a corner, or a corner portion thereof, which may block the angled implant material.

    Abstract translation: 形成在第一导电类型的衬底上的新型像素传感器结构包括第二导电类型的光敏器件和第一导电类型的表面钉扎层。 在光敏器件钉扎层附近形成隔离结构。 隔离结构包括掺杂区域，该掺杂剂区域包括沿着隔离结构的侧壁选择性地形成的第一导电类型的材料，其适于将表面钉扎层电耦合到下面的衬底。 用于形成沿着隔离结构的侧壁选择性地形成的掺杂剂区域的相应方法包括外扩散工艺，由此在退火期间，存在于沿隔离结构中的选定部分形成的掺杂材料层中的掺杂剂材料被驱动到下面的衬底中。 替代地或结合地，隔离结构侧壁中的掺杂剂材料的成角度的离子注入可以通过首先制造光致抗蚀剂层并通过去除可能阻挡成角度的植入材料的角部或其角部来减小其尺寸来执行。

    Methods for enhancing quality of pixel sensor image frames for global shutter imaging
    78.
    发明授权
    Methods for enhancing quality of pixel sensor image frames for global shutter imaging 有权
    用于提高全局快门成像的像素传感器图像帧质量的方法

    公开(公告)号：US08681254B2

    公开(公告)日：2014-03-25

    申请号：US13283819

    申请日：2011-10-28

    Applicant: John J. Ellis-Monaghan ,  Mark D. Jaffe

    Inventor： John J. Ellis-Monaghan ,  Mark D. Jaffe

    IPC: H04N3/14 ,  H04N5/335 ,  H04N9/64 ,  H01L31/062 ,  H01L31/113

    CPC classification number: H04N5/361 ,  H04N5/359

    Abstract: The image qualify of an image frame from a CMOS image sensor array operated in global shutter mode may be enhanced by dispersing or randomizing the noise introduced by leakage currents from floating drains among the rows of the image frame. Further, the image quality may be improved by accounting for time dependent changes in the output of dark pixels in dark pixel rows or dark pixel columns. In addition, voltage and time dependent changes in the output of dark pixels may also be measured to provide an accurate estimate of the noise introduced to the charge held in the floating drains. Such methods may be employed individually or in combination to improve the quality of the image.

    Abstract translation: 来自在全球快门模式下操作的CMOS图像传感器阵列的图像帧的图像限定可以通过将来自浮动排水口的泄漏电流引入的噪声分散或随机化在图像帧的行中来增强。 此外，通过考虑暗像素行或暗像素列中的暗像素的输出中的时间依赖性变化，可以提高图像质量。 此外，还可以测量暗像素的输出中的电压和时间相关的变化，以提供引入到浮动排水管中的电荷的噪声的准确估计。 这样的方法可以单独使用或组合使用以提高图像的质量。

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