公开(公告)号：US5804498A

公开(公告)日：1998-09-08

申请号：US907265

申请日：1997-08-06

申请人： Syun-Ming Jang ,  Lu-Min Liu ,  Lung Chen

发明人： Syun-Ming Jang ,  Lu-Min Liu ,  Lung Chen

IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/02164 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/31612 ,  H01L21/76819

摘要： An improved method of ozone-TEOS deposition with reduced pattern sensitivity and improved gap filling capability is described. Semiconductor device structures are provided in and on a semiconductor substrate. A conducting layer is deposited overlying the surfaces of the semiconductor device structures and patterned to form conducting lines wherein the conducting lines are dense in some portions of the semiconductor substrate and sparse in other portions of the substrate and wherein gaps are formed between the conducting lines. A nucleation layer is formed by depositing a first pattern sensitivity reducing layer over the surfaces of the conducting layer and then depositing a first oxide layer overlying the first dielectric layer. A second oxide layer is deposited over the nucleation layer wherein the gap is filled by the second oxide layer and the fabrication of integrated circuit is completed.

摘要翻译： 描述了改进的臭氧-TEOS沉积方法，其具有降低的图案灵敏度和改进的间隙填充能力。 半导体器件结构设置在半导体衬底中和半导体衬底上。 导电层沉积在半导体器件结构的表面上并被图案化以形成导电线，其中导电线在半导体衬底的一些部分是致密的并且在衬底的其它部分中稀疏，并且其中在导线之间形成间隙。 通过在导电层的表面上沉积第一图案敏感性降低层然后沉积覆盖在第一介电层上的第一氧化物层来形成成核层。 第二氧化物层沉积在成核层上，其中间隙被第二氧化物层填充，并且集成电路的制造完成。

公开(公告)号：US5904573A

公开(公告)日：1999-05-18

申请号：US620182

申请日：1996-03-22

申请人： Syun-Ming Jang ,  Lung Chen ,  Chen-Hua D.. Yu

发明人： Syun-Ming Jang ,  Lung Chen ,  Chen-Hua D.. Yu

IPC分类号： C23C16/40 ,  H01L21/316

CPC分类号： H01L21/02164 ,  C23C16/402 ,  H01L21/0214 ,  H01L21/02274 ,  H01L21/31612

摘要： An improvement in the properties of etch rate, mechanical stress, and chemical resistance of silicon layers obtained by plasma-enhanced chemical vapor deposition from mixtures of reactive gases such as oxygen and tetraethoxysilane is achieved by adding nitrogen gas to the reactive gas mixture. The addition of nitrogen gas is effective in improving the cited properties of the silicon oxide layers without altering the basic properties of the deposition process or degrading the other desirable properties of the silicon oxide layers in any substantial manner.

摘要翻译： 通过向反应气体混合物中加入氮气，可以实现通过等离子体增强化学气相沉积从反应性气体如氧气和四乙氧基硅烷的混合物获得的硅层的蚀刻速率，机械应力和耐化学性的改善。 氮气的添加在改善沉积工艺的基本性能或以任何实质的方式降低氧化硅层的其它所需性能的同时有效地改善了氧化硅层的引用性能。

公开(公告)号：US09647066B2

公开(公告)日：2017-05-09

申请号：US13454960

申请日：2012-04-24

申请人： Chang-Shen Lu ,  Chih-Tang Peng ,  Tai-Chun Huang ,  Pei-Ren Jeng ,  Hao-Ming Lien ,  Yi-Hung Lin ,  Tze-Liang Lee ,  Syun-Ming Jang

发明人： Chang-Shen Lu ,  Chih-Tang Peng ,  Tai-Chun Huang ,  Pei-Ren Jeng ,  Hao-Ming Lien ,  Yi-Hung Lin ,  Tze-Liang Lee ,  Syun-Ming Jang

IPC分类号： H01L27/088 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/20

CPC分类号： H01L29/10 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/6681 ,  H01L29/785

摘要： A FinFET device may include a dummy FinFET structure laterally adjacent an active FinFET structure to reduce stress imbalance and the effects of stress imbalance on the active FinFET structure. The FinFET device comprises an active FinFET comprising a plurality of semiconductor fins, and a dummy FinFET comprising a plurality of semiconductor fins. The active FinFET and the dummy FinFET are laterally spaced from each other by a spacing that is related to the fin pitch of the active FinFET.

公开(公告)号：US09269612B2

公开(公告)日：2016-02-23

申请号：US13434691

申请日：2012-03-29

申请人： Chien-An Chen ,  Wen-Jiun Liu ,  Chun-Chieh Lin ,  Hung-Wen Su ,  Ming-Hsing Tsai ,  Syun-Ming Jang

发明人： Chien-An Chen ,  Wen-Jiun Liu ,  Chun-Chieh Lin ,  Hung-Wen Su ,  Ming-Hsing Tsai ,  Syun-Ming Jang

IPC分类号： H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76877 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76864 ,  H01L21/76882 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure includes a first trench and a second trench. The second trench is wider than the first trench. Both trenches are lined with a diffusion barrier layer, and a first conductive layer is deposited over the diffusion barrier layer. A metal cap layer is deposited over the first conductive layer. A second conductive layer is deposited over the metal cap layer in the second trench.

摘要翻译： 互连结构包括第一沟槽和第二沟槽。 第二沟槽比第一沟槽宽。 这两个沟槽都带有扩散阻挡层，并且第一导电层沉积在扩散阻挡层上。 在第一导电层上沉积金属覆盖层。 第二导电层沉积在第二沟槽中的金属覆盖层上。

公开(公告)号：US09029260B2

公开(公告)日：2015-05-12

申请号：US13161701

申请日：2011-06-16

申请人： Chun Chieh Lin ,  Hung-Wen Su ,  Minghsing Tsai ,  Syun-Ming Jang

发明人： Chun Chieh Lin ,  Hung-Wen Su ,  Minghsing Tsai ,  Syun-Ming Jang

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76877 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/511 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.

摘要翻译： 本公开提供了制造半导体器件的方法。 该方法包括形成具有多个第一开口的图案化电介质层。 该方法包括在图案化的介电层上形成导电衬垫层，导电衬垫层部分填充第一开口。 该方法包括在第一开口之外的导电衬垫层的部分上形成沟槽掩模层，从而形成多个第二开口，其中一部分形成在第一开口上。 该方法包括在第一开口中沉积导电材料以形成多个通孔，并且在第二开口中形成多个金属线。 该方法包括去除沟槽掩模层。

公开(公告)号：US08932962B2

公开(公告)日：2015-01-13

申请号：US13442040

申请日：2012-04-09

申请人： Weibo Yu ,  Kuo Bin Huang ,  Chao-Cheng Chen ,  Syun-Ming Jang

发明人： Weibo Yu ,  Kuo Bin Huang ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC分类号： H01L21/302

CPC分类号： H01L21/6708 ,  H01L21/30608 ,  H01L21/31111 ,  H01L21/67109 ,  H01L22/12 ,  H01L22/20

摘要： A method and apparatus for dispensing a liquid etchant onto a wafer dispenses the liquid etchant onto a wafer using a scanning dispensing nozzle while controlling the dispensing temperature of the etchant in real time as a function of the radial position of the dispensing nozzle over the wafer. The dispensing temperature of the etchant is controlled to enhance the effectiveness of the etchant and thus compensate for the lower etching rate zones in the wafer.

摘要翻译： 用于将液体蚀刻剂分配到晶片上的方法和设备使用扫描分配喷嘴将液体蚀刻剂分配到晶片上，同时根据分配喷嘴在晶片上的径向位置实时控制蚀刻剂的分配温度。 控制蚀刻剂的分配温度以提高蚀刻剂的有效性，从而补偿晶片中较低的蚀刻速率区域。

公开(公告)号：US08609484B2

公开(公告)日：2013-12-17

申请号：US12617004

申请日：2009-11-12

申请人： Lee-Wee Tao ,  Han-Guan Chew ,  Harry Hak-Lay Chuang ,  Syun-Ming Jang

发明人： Lee-Wee Tao ,  Han-Guan Chew ,  Harry Hak-Lay Chuang ,  Syun-Ming Jang

IPC分类号： H01L29/00

CPC分类号： H01L29/7845 ,  H01L21/28518 ,  H01L21/3215 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66507 ,  H01L29/66545

摘要： The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a metal gate on the substrate, the metal gate having a first gate resistance, removing a portion of the metal gate thereby forming a trench; and forming a conductive structure within the trench such that a second gate resistance of the conductive structure and remaining portion of the metal gate is lower than the first gate resistance.

摘要翻译： 本公开提供一种制造半导体器件的方法，该半导体器件包括提供半导体衬底，在衬底上形成金属栅极，具有第一栅极电阻的金属栅极，去除金属栅极的一部分从而形成沟槽; 以及在所述沟槽内形成导电结构，使得所述导电结构的第二栅极电阻和所述金属栅极的剩余部分低于所述第一栅极电阻。

公开(公告)号：US20130157462A1

公开(公告)日：2013-06-20

申请号：US13328680

申请日：2011-12-16

申请人： Chia Ying Lee ,  Chih-Yuan Ting ,  Jyu-Horng Shieh ,  Minghsing Tsai ,  Syun-Ming Jang

发明人： Chia Ying Lee ,  Chih-Yuan Ting ,  Jyu-Horng Shieh ,  Minghsing Tsai ,  Syun-Ming Jang

IPC分类号： H01L21/28 ,  H01L21/302

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32

摘要： The present disclosure provides a method including providing a semiconductor substrate and forming a first layer and a second layer on the semiconductor substrate. The first layer is patterned to provide a first element, a second element, and a space interposing the first and second elements. Spacer elements are then formed on the sidewalls on the first and second elements of the first layer. Subsequently, the second layer is etched using the spacer elements and the first and second elements as a masking element.

公开(公告)号：US08330275B2

公开(公告)日：2012-12-11

申请号：US13290811

申请日：2011-11-07

申请人： Hui-Lin Chang ,  Hung Chun Tsai ,  Yung-Cheng Lu ,  Syun-Ming Jang

发明人： Hui-Lin Chang ,  Hung Chun Tsai ,  Yung-Cheng Lu ,  Syun-Ming Jang

IPC分类号： H01L23/52

CPC分类号： H01L23/53238 ,  H01L21/28556 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76886 ,  H01L21/76889 ,  H01L23/528 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

摘要： A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, a conductive layer is located within a dielectric layer and a top surface of the conductive layer has either a recess, a convex surface, or is planar. An alloy layer overlies the conductive layer and is a silicide alloy having a first material from the conductive layer and a second material of germanium, arsenic, tungsten, or gallium.

摘要翻译： 提供了形成在第一介电层中的铜互连结构的盖层。 在一个实施例中，导电层位于电介质层内，并且导电层的顶表面具有凹陷，凸面或平面。 合金层覆盖在导电层上，并且是具有来自导电层的第一材料和锗，砷，钨或镓的第二材料的硅化物合金。

公开(公告)号：US20120292767A1

公开(公告)日：2012-11-22

申请号：US13561826

申请日：2012-07-30

申请人： Hsien-Ming Lee ,  Minghsing Tsai ,  Syun-Ming Jang

发明人： Hsien-Ming Lee ,  Minghsing Tsai ,  Syun-Ming Jang

IPC分类号： H01L21/768 ,  H01L23/535

CPC分类号： H01L21/76856 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76873

摘要： A method for fabricating an integrated circuit structure and the resulting integrated circuit structure are provided. The method includes forming a low-k dielectric layer; form an opening in the low-k dielectric layer; forming a barrier layer covering a bottom and sidewalls of the low-k dielectric layer; performing a treatment to the barrier layer in an environment comprising a treatment gas; and filling the opening with a conductive material, wherein the conductive material is on the barrier layer.

摘要翻译： 提供一种用于制造集成电路结构的方法和所得到的集成电路结构。 该方法包括形成低k电介质层; 在低k电介质层中形成开口; 形成覆盖所述低k电介质层的底部和侧壁的阻挡层; 在包括处理气体的环境中对阻挡层进行处理; 并用导电材料填充开口，其中导电材料在阻挡层上。