公开(公告)号：US07195976B2

公开(公告)日：2007-03-27

申请号：US10851350

申请日：2004-05-24

申请人： Tetsuo Adachi ,  Masataka Kato ,  Toshiakl Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

发明人： Tetsuo Adachi ,  Masataka Kato ,  Toshiakl Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

IPC分类号： H01L21/8247

CPC分类号： H01L21/28273 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3454 ,  H01L21/28061 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833

摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistor can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

摘要翻译： 一种半导体器件，其特别是确保器件的可靠性，特别是在微细的区域中并且能够实现大的电容和高速操作，具有在半导体衬底的主表面的第一区域中包括栅绝缘膜，浮栅电极， 层间绝缘膜，控制栅极电极以及以矩阵形式布置的第二导电类型的源极和漏极区域，具有用于隔离存储单元的浅隔离结构。 当使用用绝缘膜掩埋的浅结构用于元件隔离时，可以防止微细区域中的隔离耐受电压降低，并且可以降低选择性晶体管的阈值电平的变化。 当通过选择性晶体管分配存储器垫中的存储单元时，可以提高存储单元的干扰电阻。

公开(公告)号：US07057230B2

公开(公告)日：2006-06-06

申请号：US10484578

申请日：2002-07-22

申请人： Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

发明人： Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

IPC分类号： H01L29/788

CPC分类号： G11C16/26 ,  G11C5/025 ,  G11C8/08 ,  G11C16/04 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H01L21/28 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7885 ,  H01L29/792

摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc

摘要翻译： 半导体器件包括多个非易失性存储单元（1）。 每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。 第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。 第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。 第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。 假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

公开(公告)号：US06972997B2

公开(公告)日：2005-12-06

申请号：US10743783

申请日：2003-12-24

申请人： Tetsuya Ishimaru ,  Nozomu Matsuzaki ,  Hitoshi Kume

发明人： Tetsuya Ishimaru ,  Nozomu Matsuzaki ,  Hitoshi Kume

IPC分类号： G11C11/34 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0433 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/518 ,  H01L29/792

摘要： Characteristics of a nonvolatile semiconductor memory device are improved. The memory cell comprises: an ONO film constituted by a silicon nitride film SIN for accumulating charge and by oxide films BOTOX and TOPOX disposed thereon and thereunder; a memory gate electrode MG disposed at an upper portion thereof; a select gate electrode SG disposed at a side portion thereof through the ONO film; a gate oxide film SGOX disposed thereunder. By applying a potential to a select gate electrode SG of a memory cell having a source region MS and a drain region MD and to the source region MS and by accelerating electrons flowing in a channel through a high electric field produced between a channel end of the select transistor and an end of an n-type doped region ME disposed under the memory gate electrode MG, hot holes are generated by impact ionization, and the hot holes are injected into a silicon nitride film SIN by a negative potential applied to the memory gate electrode MG, and thereby an erase operation is performed.

摘要翻译： 提高了非易失性半导体存储器件的特性。 存储单元包括：由用于累积电荷的氮化硅膜SIN和其上设置的氧化膜BOTOX和TOPOX构成的ONO膜; 设置在其上部的存储栅极电极MG; 通过ONO膜设置在其侧部的选择栅电极SG; 设置在其下方的栅氧化膜SGOX。 通过向具有源极区域MS和漏极区域MD的存储单元的选择栅极SG施加电位，并且通过在通道的沟道端之间产生的高电场加速在沟道中流动的电子， 选择晶体管和设置在存储栅电极MG下方的n型掺杂区ME的端部，通过冲击电离产生热孔，并且通过施加到存储栅的负电位将热孔注入氮化硅膜SIN 电极MG，从而进行擦除操作。

公开(公告)号：US20050090058A1

公开(公告)日：2005-04-28

申请号：US10954102

申请日：2004-09-30

申请人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

发明人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

IPC分类号： H01M10/0525 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C27/00 ,  H01L21/00 ,  H01L21/28 ,  H01L21/283 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/76 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/94 ,  H01L31/062 ,  H01L31/119 ,  H01M2/16

CPC分类号： H01L21/28273 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3454 ,  H01L21/28061 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833

摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

公开(公告)号：US06842376B2

公开(公告)日：2005-01-11

申请号：US10638491

申请日：2003-08-12

申请人： Nozomu Matsuzaki ,  Kazuyoshi Shiba ,  Yasuhiro Taniguchi ,  Toshihiro Tanaka ,  Yutaka Shinagawa

发明人： Nozomu Matsuzaki ,  Kazuyoshi Shiba ,  Yasuhiro Taniguchi ,  Toshihiro Tanaka ,  Yutaka Shinagawa

IPC分类号： G11C16/06 ,  G11C8/08 ,  G11C16/02 ,  G11C16/12 ,  G11C16/34 ,  G11C16/04

CPC分类号： G11C16/3409 ,  G11C8/08 ,  G11C16/12 ,  G11C16/3404

摘要： A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.

摘要翻译： 一种用于在非易失性半导体存储器件的擦除处理中在预定电平上建立字线的阈值电压的方法，以加速擦除处理。 为每个字线提供字锁存电路，并且在所选择的存储器块中为每个字线管理每个存储器单元的阈值电压。 每个字锁存电路由多个字线共享，以便减少所需的芯片面积。 为每个完成的非易失性存储器设置重写电压，并且电压信息被存储在非易失性存储器的引导区域中，使得每当系统供电时，系统识别电压。

公开(公告)号：US06444554B1

公开(公告)日：2002-09-03

申请号：US10011731

申请日：2001-12-11

申请人： Tetsuo Adachi ,  Masataka Kato ,  Toshiakl Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

发明人： Tetsuo Adachi ,  Masataka Kato ,  Toshiakl Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

IPC分类号： H01L21283

CPC分类号： H01L21/28273 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3454 ,  H01L21/28061 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833

摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

摘要翻译： 一种半导体器件，其特别是确保器件的可靠性，特别是在微细的区域中并且能够实现大的电容和高速操作，具有在半导体衬底的主表面的第一区域中包括栅绝缘膜，浮栅电极， 层间绝缘膜，控制栅极电极以及以矩阵形式布置的第二导电类型的源极和漏极区域，具有用于隔离存储单元的浅隔离结构。 当使用用绝缘膜掩埋的浅结构用于元件隔离时，可以防止微细区域中的隔离耐受电压降低，并且可以降低选择性晶体管的阈值电平的变化。 当通过选择性晶体管分配存储器垫中的存储单元时，可以提高存储单元的干扰电阻。

公开(公告)号：US08866120B2

公开(公告)日：2014-10-21

申请号：US13314165

申请日：2011-12-07

申请人： Yuichi Matsui ,  Nozomu Matsuzaki ,  Norikatsu Takaura ,  Naoki Yamamoto ,  Hideyuki Matsuoka ,  Tomio Iwasaki

发明人： Yuichi Matsui ,  Nozomu Matsuzaki ,  Norikatsu Takaura ,  Naoki Yamamoto ,  Hideyuki Matsuoka ,  Tomio Iwasaki

IPC分类号： H01L47/00 ,  H01L45/00

CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

摘要： Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.

公开(公告)号：US08674419B2

公开(公告)日：2014-03-18

申请号：US12838598

申请日：2010-07-19

申请人： Nozomu Matsuzaki ,  Hiroyuki Mizuno ,  Masashi Horiguchi

发明人： Nozomu Matsuzaki ,  Hiroyuki Mizuno ,  Masashi Horiguchi

IPC分类号： H01L29/72

CPC分类号： H01L21/823857 ,  B82Y99/00 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/0883 ,  H01L29/42364 ,  Y10S438/981 ,  Y10S977/936

摘要： The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.

摘要翻译： 半导体集成电路器件在相同的硅衬底上采用具有在源极和栅极之间或其漏极和栅极之间流动的不同大小的隧道电流的多种MOS晶体管。 这些MOS晶体管包括隧道电流增加的MOS晶体管，其中至少一个用于构成器件的主电路。 多种MOS晶体管还包括隧道电流减少或耗尽的MOS晶体管，其中至少一个用于控制电路。 该控制电路插入在主电路和两个电源单元中的至少一个之间。

公开(公告)号：US08482961B2

公开(公告)日：2013-07-09

申请号：US13456195

申请日：2012-04-25

申请人： Satoru Hanzawa ,  Fumihiko Nitta ,  Nozomu Matsuzaki ,  Toshihiro Tanaka

发明人： Satoru Hanzawa ,  Fumihiko Nitta ,  Nozomu Matsuzaki ,  Toshihiro Tanaka

IPC分类号： G11C11/00

CPC分类号： G11C5/06 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/144

摘要： In a semiconductor device including a memory cell array formed of memory cells using a storage element by a variable resistor and a select transistor, a buffer cell is arranged between a sense amplifier and the memory cell array and between a word driver and the memory cell array. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.

公开(公告)号：US08017986B2

公开(公告)日：2011-09-13

申请号：US12718111

申请日：2010-03-05

申请人： Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

发明人： Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

IPC分类号： H01L29/788

CPC分类号： G11C16/26 ,  G11C5/025 ,  G11C8/08 ,  G11C16/04 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H01L21/28 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7885 ,  H01L29/792

摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc

摘要翻译： 半导体器件包括多个非易失性存储单元（1）。 每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。 第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。 第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。 第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。 假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc