公开(公告)号：US06249184B1

公开(公告)日：2001-06-19

申请号：US09452029

申请日：1999-11-30

申请人： Marco Corsi

发明人： Marco Corsi

IPC分类号： H03F345

CPC分类号： H03F3/4517 ,  H03F3/45094 ,  H03F3/45587 ,  H03F2203/45406 ,  H03F2203/45424 ,  H03F2203/45431

摘要： A rail-to-rail input stage (20) for an operational amplifier having a constant transconductance (Gm) over a common mode range. The input stage has a cross-coupled quad circuit (Q9, Q10, Q15, Q16) having an essentially infinite transconductance, and pair of transistors (Q5, 6) running at the same current as input transistors (Q1, Q2) when active, whereby the pair of transistors (Q5, Q6) establish a constant transconductance of the input stage (20).

摘要翻译： 一种用于在共模范围内具有恒定跨导（Gm）的运算放大器的轨到轨输入级（20）。 输入级具有具有基本上无限跨导的交叉耦合四电路（Q9，Q10，Q15，Q16）以及当与有源时在与输入晶体管（Q1，Q2）相同的电流下运行的一对晶体管（Q5,6） 由此一对晶体管（Q5，Q6）建立输入级（20）的恒定跨导。

公开(公告)号：US06188211B1

公开(公告)日：2001-02-13

申请号：US09309991

申请日：1999-05-11

申请人： Gabriel Alfonso Rincon-Mora ,  Marco Corsi

发明人： Gabriel Alfonso Rincon-Mora ,  Marco Corsi

IPC分类号： G05F1575

CPC分类号： G05F1/575 ,  G05F3/247 ,  G05F3/267

摘要： A low drop-out (LDO) voltage regulator (10) and system (100) including the same are disclosed. An error amplifier (38) controls the gate voltage of a source follower transistor (24) in response to the difference between a feedback voltage (VFB) from the output (VOUT) and a reference voltage (VREF). The source of the source follower transistor (24) is connected to the gates of an output transistor (12), which drives the output (VOUT) from the input voltage (VIN) in response to the source follower transistor (24). A current mirror transistor (14) has its gate also connected to the gate of the output transistor (12), and mirrors the output current at a much reduced ratio. The mirror current is conducted through network of transistors (18, 22), and controls the conduction of a first feedback transistor (28) and a second feedback transistor (35) which are each connected to the source of the source follower transistor (24) and in parallel with a weak current source (34). The response of the first feedback transistor (28) is slowed by a resistor (32) and capacitor (30), while the second feedback transistor (35) is not delayed. As such, the second feedback transistor (35) assists transient response, particularly in discharging the gate capacitance of the output transistor (12), while the first feedback transistor (28) partially cancels load regulation effects.

摘要翻译： 公开了包括其的低压差（LDO）稳压器（10）和系统（100）。 误差放大器（38）响应于来自输出（VOUT）的反馈电压（VOUT）与参考电压（VREF）之间的差异来控制源极跟随器晶体管（24）的栅极电压。 源极跟随器晶体管（24）的源极连接到输出晶体管（12）的栅极，其响应于源极跟随器晶体管（24）而驱动输出（VOUT）与输入电压（VIN）。 电流镜晶体管（14）的栅极也连接到输出晶体管（12）的栅极，并以大大降低的比率反射输出电流。 镜电流通过晶体管（18,22）的网络传导，并且控制每个连接到源极跟随器晶体管（24）的源极的第一反馈晶体管（28）和第二反馈晶体管（35）的导通， 并与弱电流源（34）并联。 第一反馈晶体管（28）的响应由电阻器（32）和电容器（30）减慢，而第二反馈晶体管（35）不被延迟。 这样，第二反馈晶体管（35）有助于瞬态响应，特别是在放电输出晶体管（12）的栅极电容时，第一反馈晶体管（28）部分地消除负载调节效应。

公开(公告)号：US6144100A

公开(公告)日：2000-11-07

申请号：US959410

申请日：1997-10-28

申请人： Chi-Cheong Shen ,  Donald C. Abbott ,  Walter Bucksch ,  Marco Corsi ,  Taylor Rice Efland ,  John P. Erdeljac ,  Louis Nicholas Hutter ,  Quang Mai ,  Konrad Wagensohner ,  Charles Edward Williams

发明人： Chi-Cheong Shen ,  Donald C. Abbott ,  Walter Bucksch ,  Marco Corsi ,  Taylor Rice Efland ,  John P. Erdeljac ,  Louis Nicholas Hutter ,  Quang Mai ,  Konrad Wagensohner ,  Charles Edward Williams

IPC分类号： H01L23/485 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L24/05 ,  H01L2224/04042 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48744 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/3025

摘要： An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A 2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.

摘要翻译： 一种具有直接在其有源电路上的接合表面（12）的集成电路器件（10），以及制造这种集成电路的方法（图2A 2E）。 为了形成接合表面（12），晶片（20）在其金属化层（21）上设有通孔（24），然后涂覆有种子金属层（25）。 电镀图案（26）形成在晶片（20）上，暴露种子金属层（25）的部分并阻挡种子金属层（25）的其余部分。 这些暴露部分镀有连续的金属层（27,28,29），由此形成具有填充通孔（24）的多个层叠堆叠（200）的接合表面（12）。 然后除去种子金属层（25）的电镀图案和非电镀部分。

公开(公告)号：US5886554A

公开(公告)日：1999-03-23

申请号：US813246

申请日：1997-03-07

申请人： Marco Corsi ,  Raghunath Cherukuri

发明人： Marco Corsi ,  Raghunath Cherukuri

IPC分类号： H03K19/003 ,  H03K5/12

CPC分类号： H03K19/00361

摘要： Slew-rate limited differential drivers are useful for reliable data transmission on longer un-terminated cables with longer stub lengths. Slew-rate limit can be achieved by the ratio of a constant current to a capacitor means. In order to have equal rise and fall times, an equal amount of current is steered into the capacitor means in opposite directions. This architecture has unequal propagation delays on the transition edges. This mismatch is directly attributable to the signal transfer in current steering means. The slew-rate limited differential driver corrects this problem by delaying the rising edge by the required amount using a second capacitor means and a diode means. And hence, the preferred embodiment has a better skew on the output.

摘要翻译： 压摆率限制差动驱动器对于具有较长短截线长度的较长非端接电缆的可靠数据传输非常有用。 可以通过恒定电流与电容器装置的比例来实现压摆率限制。 为了具有相同的上升和下降时间，将相等量的电流转向相反方向的电容器装置。 这种结构在过渡边缘上具有不相等的传播延迟。 这种不匹配直接归因于当前转向装置中的信号传递。 转换速率限制差分驱动器通过使用第二电容器装置和二极管装置将上升沿延迟所需量来校正该问题。 因此，优选实施例在输出上具有更好的倾斜。

公开(公告)号：US5861736A

公开(公告)日：1999-01-19

申请号：US348670

申请日：1994-12-01

申请人： Marco Corsi ,  Nicolas Salamina ,  Jeffrey W. Sanders ,  Michael R. Kay

发明人： Marco Corsi ,  Nicolas Salamina ,  Jeffrey W. Sanders ,  Michael R. Kay

IPC分类号： H02J1/00 ,  G05F1/56 ,  G05F1/575

CPC分类号： G05F1/56

摘要： A voltage regulator circuit (10) is provided. Regulator circuit (10) includes an amplifier (18) with an emitter follower output stage (26). Emitter follower stage (26) is coupled to a gate of a PMOS transistor (28). The source of transistor (28) is coupled to an input voltage at a power supply rail (12). Regulator (10) provides an output at node (14) at a drain of transistor (28). The output at node (14) is divided by resistors (30 and 34) and provided in a negative feedback loop to an input of amplifier (18). A reference voltage (22) is also provided to a second input of amplifier (18) such that the output at node (14) is a regulated voltage.

摘要翻译： 提供了一种电压调节器电路（10）。 调节器电路（10）包括具有发射极跟随器输出级（26）的放大器（18）。 发射极跟随器级（26）耦合到PMOS晶体管（28）的栅极。 晶体管（28）的源极耦合到电源轨（12）处的输入电压。 调节器（10）在晶体管（28）的漏极处的节点（14）处提供输出。 节点（14）处的输出由电阻（30和34）分压，并以负反馈回路提供给放大器（18）的输入。 参考电压（22）也被提供给放大器（18）的第二输入，使得节点（14）处的输出是调节电压。

公开(公告)号：US5767703A

公开(公告)日：1998-06-16

申请号：US818206

申请日：1997-03-14

申请人： Frank Fattori ,  Marco Corsi

发明人： Frank Fattori ,  Marco Corsi

IPC分类号： G06F13/40 ,  H03K19/003 ,  H04L25/02 ,  H03K3/00

CPC分类号： H04L25/0282 ,  G06F13/4072 ,  H03K19/00353 ,  H03K19/00376 ,  H04L25/028 ,  H04L25/029 ,  H04L25/0272

摘要： This invention relates to differential bus drivers for use in, for example, communication systems. The driver achieves highly symmetrical wave forms at the output stage for both high and low side drivers. In addition, the layout of components of the high and low side drivers is substantially identical which allows production of the driver as an integrated circuit with a simple layout.

摘要翻译： 本发明涉及用于例如通信系统的差分总线驱动器。 驱动器在高低侧驱动器的输出级可实现高度对称的波形。 此外，高侧和低侧驱动器的部件的布局基本相同，这允许以简单的布局生产作为集成电路的驱动器。

公开(公告)号：US09222802B2

公开(公告)日：2015-12-29

申请号：US13433546

申请日：2012-03-29

申请人： Sriram Narayanan ,  David Louis Freeman ,  Marco Corsi

发明人： Sriram Narayanan ,  David Louis Freeman ,  Marco Corsi

IPC分类号： G06F15/00 ,  G01D3/10

CPC分类号： G01D3/10 ,  G01D18/00

摘要： A sensor power management arrangement includes a signal processing circuit configured to receive signal from a sensor, to test the signal against at least one criterion, and to pass the signal for further processing in response to the signal passing the at least one criterion. In this way, only signals that are of a sufficient importance or significance will consume the maximum amount of processing energy and through processing by later processes or circuitry. Should a signal from a sensor not be strong enough or meet other criteria, power will not be wasted in preparing that signal for provision to the microcontroller or microprocessor. Additional flexibility in the sensor power management can be realized by adjusting the criteria against which the sensor signal is compared based on a status of the sensor apparatus.

摘要翻译： 传感器电源管理装置包括信号处理电路，其被配置为从传感器接收信号，以针对至少一个准则测试信号，并且响应于通过所述至少一个准则的信号而传递用于进一步处理的信号。 以这种方式，仅具有足够重要性或重要性的信号将消耗最大量的处理能量并且通过后续处理或电路的处理。 如果来自传感器的信号不够牢固或符合其他标准，则在准备将信号提供给微控制器或微处理器时，功率不会被浪费。 基于传感器装置的状态，可以通过调整传感器信号进行比较的标准来实现传感器功率管理中的额外的灵活性。

公开(公告)号：US09013339B2

公开(公告)日：2015-04-21

申请号：US13551950

申请日：2012-07-18

申请人： Robert F. Payne ,  Marco Corsi

发明人： Robert F. Payne ,  Marco Corsi

IPC分类号： H03M1/00 ,  H03M1/08 ,  H03M1/12

CPC分类号： H03M1/08 ,  H03M1/1215

摘要： To date, bandwidth mismatch within time-interleaved (TI) analog-to-digital converters (ADCs) has been largely ignored because compensation for bandwidth mismatch is performed by digital post-processing, namely finite impulse response filters. However, the lag from digital post-processing is prohibitive in high speed systems, indicating a need for blind mismatch compensation. Even with blind bandwidth mismatch estimation, though, adjustment of the filter characteristics of track-and-hold (T/H) circuits within the TI ADCs can be difficult. Here, a T/H circuit architecture is provided that uses variations of the gate voltage of a sampling switch (which varies the “on” resistance of the sampling switch) to change the bandwidth of the T/H circuits so as to precisely match the bandwidths.

摘要翻译： 到目前为止，时间交织（TI）模数转换器（ADC）中的带宽不匹配已被大大忽略，因为通过数字后处理（即有限脉冲响应滤波器）执行带宽不匹配的补偿。 然而，数字后处理的滞后在高速系统中是禁止的，表明需要盲目错配补偿。 即使使用盲带宽失配估计，TI ADC内的跟踪保持（T / H）电路的滤波特性的调整也是困难的。 这里，提供了使用采样开关的栅极电压的变化（其改变采样开关的“开”电阻）的T / H电路架构，以改变T / H电路的带宽，以便精确匹配 带宽。

公开(公告)号：US08970411B2

公开(公告)日：2015-03-03

申请号：US13601795

申请日：2012-08-31

申请人： Baher S. Haroun ,  Venkatesh Srinivasan ,  Patrick Satarzadeh ,  Marco Corsi

发明人： Baher S. Haroun ,  Venkatesh Srinivasan ,  Patrick Satarzadeh ,  Marco Corsi

IPC分类号： H03M3/00

CPC分类号： H03M3/344 ,  H03M3/458

摘要： Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.

摘要翻译： 传统上，流水线连续时间（CT）Σ-Δ调制器（SDM）已经难以构建，至少部分是由于校准管道的困难。 然而，这里提供了一种流水线CT SDM，其具有有助于被校准的架构。 也就是说，该系统包括数字滤波器和其他可调整的特征，以解决输入不平衡误差以及量化泄漏噪声。

公开(公告)号：US20130265732A1

公开(公告)日：2013-10-10

申请号：US13439557

申请日：2012-04-04

申请人： Juan A. Herbsommer ,  Robert F. Payne ,  Marco Corsi ,  Baher S. Haroun ,  Hassan Ali

发明人： Juan A. Herbsommer ,  Robert F. Payne ,  Marco Corsi ,  Baher S. Haroun ,  Hassan Ali

IPC分类号： H05K1/11 ,  H05K1/18

CPC分类号： H05K1/0239 ,  G02B6/12004 ,  G02B6/1228 ,  H01L2223/6627 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01P3/121 ,  H01P3/16 ,  H05K1/0243 ,  H05K1/025 ,  H05K1/0274 ,  H05K1/115 ,  H05K1/18 ,  H05K2201/0187 ,  H05K2201/037 ,  H05K2201/09618 ,  H05K2201/10098

摘要： An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board is also secured to the package substrate. A dielectric waveguide is secured to the circuit board. The dielectric waveguide has a dielectric core that extends into a transition region located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide.

摘要翻译： 提供了一种装置。 存在具有封装基板和集成电路（IC）的电路组件。 封装衬底具有微带线，并且IC被固定到封装衬底并且电耦合到微带线。 电路板也固定到封装衬底。 介质波导固定在电路板上。 电介质波导具有延伸到位于电介质波导和微带线之间的过渡区域的介质芯，并且微带线被配置为与介质波导形成通信链路。