公开(公告)号：US20180190483A1

公开(公告)日：2018-07-05

申请号：US15652413

申请日：2017-07-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Alexander Reznicek ,  Dominic J. Schepis ,  Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi

IPC: H01L21/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/31 ,  H01L21/311 ,  H01L29/165 ,  H01L29/10 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L21/02647 ,  H01L21/0237 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/31 ,  H01L21/311 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66446 ,  H01L29/66795 ,  H01L29/785

Abstract: One aspect of the disclosure relates to a method of forming a semiconductor structure. The method may include: forming a set of openings within a substrate; forming an insulator layer within each opening in the set of openings; recessing the substrate between adjacent openings containing the insulator layer in the set of openings to form a set of insulator pillars on the substrate; forming sigma cavities within the recessed substrate between adjacent insulator pillars in the set of insulator pillars; and filling the sigma cavities with a semiconductor material over the recessed substrate between adjacent insulator pillars.

公开(公告)号：US09966457B2

公开(公告)日：2018-05-08

申请号：US15073740

申请日：2016-03-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dominic J. Schepis ,  Alexander Reznicek ,  Pranita Kerber ,  Qiqing C. Ouyang

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/321 ,  H01L21/306 ,  H01L21/324 ,  H01L21/768

CPC classification number: H01L29/66818 ,  H01L21/30604 ,  H01L21/321 ,  H01L21/324 ,  H01L21/76897 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Aspects of the present disclosure include finFET structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area, and a terminal area laterally distal to the gate area, a sacrificial gate positioned on the gate area of the semiconductor fin, and an insulator positioned on the terminal area of the semiconductor fin; removing the sacrificial gate to expose the gate area of the semiconductor fin; increasing or reducing a cross-sectional area of the gate area of the semiconductor fin; and forming a transistor gate on the gate area of the semiconductor fin.

公开(公告)号：US09905692B2

公开(公告)日：2018-02-27

申请号：US15160099

申请日：2016-05-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Alexander Reznicek ,  Shogo Mochizuki ,  Veeraraghavan S. Basker ,  Nicolas L. Breil ,  Oleg Gluschenkov

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: Fabrication method for a semiconductor device and structure are provided, which includes: providing an isolation layer at least partially disposed adjacent to at least one sidewall of a fin structure extended above a substrate structure, the fin structure including a channel region; recessing an exposed portion of the fin structure to define a residual stress to be induced into the channel region of the fin structure, wherein upper surfaces of a recessed fin portion and the isolation layer are coplanar with each other; and epitaxially growing a semiconductor material from the recessed exposed portion of the fin structure to form at least one of a source region and a drain region of the semiconductor device.

公开(公告)号：US09812575B1

公开(公告)日：2017-11-07

申请号：US15266092

申请日：2016-09-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Alexander Reznicek ,  Pouya Hashemi ,  Kangguo Cheng ,  Dominic J. Schepis

IPC: H01L29/78 ,  H01L29/165 ,  H01L23/528 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/845 ,  H01L23/5283 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/66545

Abstract: FinFET structures include a stacked fin architecture formed on a semiconductor substrate. The stacked fin architecture includes a template semiconductor layer disposed on the substrate beneath the semiconductor fins that is used as an etch stop during fin formation and to form a laterally-extending epitaxial layer for contacting the bottom tier of fins within the stack.

公开(公告)号：US20170271146A1

公开(公告)日：2017-09-21

申请号：US15075668

申请日：2016-03-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Alexander Reznicek ,  Dominic J. Schepis ,  Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/06 ,  H01L21/31 ,  H01L21/311

CPC classification number: H01L21/0243 ,  H01L21/0237 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/31 ,  H01L21/311 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66446 ,  H01L29/66795 ,  H01L29/785

Abstract: One aspect of the disclosure relates to a method of forming a semiconductor structure. The method may include: forming a set of openings within a substrate; forming an insulator layer within each opening in the set of openings; recessing the substrate between adjacent openings containing the insulator layer in the set of openings to form a set of insulator pillars on the substrate; forming sigma cavities within the recessed substrate between adjacent insulator pillars in the set of insulator pillars; and filling the sigma cavities with a semiconductor material over the recessed substrate between adjacent insulator pillars.

公开(公告)号：US09728626B1

公开(公告)日：2017-08-08

申请号：US15251435

申请日：2016-08-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dominic J. Schepis ,  Charan V. Surisetty ,  Kangguo Cheng ,  Alexander Reznicek

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L29/32 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/02636 ,  H01L21/30604 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/32 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/785

Abstract: A FinFET includes a fin and a conductive gate surrounding a top channel region of the fin, the channel region of the fin being filled with an epitaxial semiconductor channel material extending below a bottom surface of the conductive gate. The top channel region of the fin includes epitaxial semiconductor channel material that is at least majority defect free, the at least a majority of defects associated with forming the epitaxial semiconductor material in the channel region being trapped below a top portion of the channel region. The FinFET may be achieved by a method, the method including providing a starting semiconductor structure, the starting semiconductor structure including a bulk semiconductor substrate, semiconductor fin(s) on the bulk semiconductor substrate and surrounded by a dielectric layer, and a dummy gate over a channel region of the semiconductor fin(s). The method further includes forming source and drain recesses adjacent the channel region, removing the dummy gate, recessing the semiconductor fin(s), the recessing leaving a fin opening above the recessed semiconductor fin(s), and growing epitaxial semiconductor channel material in the fin opening, such that at least a majority of defects associated with the growing are trapped at a bottom portion of the at least one fin opening.

公开(公告)号：US09673196B2

公开(公告)日：2017-06-06

申请号：US14559951

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/336 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L29/167 ,  H01L21/02 ,  H01L21/84

CPC classification number: H01L27/088 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/28008 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/84 ,  H01L29/167 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method including providing a semiconductor substrate including a first semiconductor device and a second semiconductor device, the first and second semiconductor devices including dummy spacers, dummy gates, and extension regions; protecting the second semiconductor device with a mask; removing the dummy spacers from the first semiconductor device; and depositing in-situ doped epitaxial regions on top of the extension regions of the first semiconductor device.

公开(公告)号：US09530843B2

公开(公告)日：2016-12-27

申请号：US14738336

申请日：2015-06-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Davood Shahrjerdi

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/324

CPC classification number: H01L29/1054 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/306 ,  H01L21/31144 ,  H01L21/324 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/78687

Abstract: A planar semiconductor device including a semiconductor on insulator (SOI) substrate with source and drain portions having a thickness of less than 10 nm that are separated by a multi-layered strained channel. The multi-layer strained channel of the SOI layer includes a first layer with a first lattice dimension that is present on the buried dielectric layer of the SOI substrate, and a second layer of a second lattice dimension that is in direct contact with the first layer of the multi-layer strained channel portion. A functional gate structure is present on the multi-layer strained channel portion of the SOI substrate. The semiconductor device having the multi-layered channel may also be a finFET semiconductor device.

Abstract translation: 一种平面半导体器件，包括绝缘体上半导体（SOI）衬底，源极和漏极部分具有由多层应变通道分离的小于10nm的厚度。 SOI层的多层应变通道包括存在于SOI衬底的掩埋介电层上的第一晶格尺寸的第一层和与第一层直接接触的第二晶格尺寸的第二层 的多层应变通道部分。 功能栅极结构存在于SOI衬底的多层应变通道部分上。 具有多层通道的半导体器件也可以是finFET半导体器件。

公开(公告)号：US09502408B2

公开(公告)日：2016-11-22

申请号：US14079733

申请日：2013-11-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Pranita Kerber ,  Qiqing C. Ouyang ,  Alexander Reznicek

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L27/0886 ,  H01L21/823431

Abstract: A method for manufacturing a fin field-effect transistor (FinFET) device, comprises forming a plurality of fins on a substrate to a first thickness, forming a sacrificial gate stack on portions of the fins, forming source drain junctions using ion implantation, forming a dielectric layer on the substrate, removing the sacrificial gate stack to expose the portions of the fins, thinning the exposed portions of the fins to a second thickness less than the first thickness, and forming a gate stack on the thinned exposed portions of the fins to replace the removed sacrificial gate stack.

Abstract translation: 一种用于制造鳍状场效应晶体管（FinFET）器件的方法，包括在衬底上形成多个翅片至第一厚度，在鳍片的部分上形成牺牲栅极叠层，使用离子注入形成源漏极结，形成 电介质层，去除牺牲栅极堆叠以暴露散热片的部分，将散热片的暴露部分减薄到小于第一厚度的第二厚度，以及在散热片的变薄的暴露部分上形成栅极堆叠 更换去除的牺牲栅极堆叠。

公开(公告)号：US09478642B2

公开(公告)日：2016-10-25

申请号：US14537832

申请日：2014-11-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Pouya Hashemi ,  Shogo Mochizuki ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/66795 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor structure, such as a FinFET, etc., includes a bi-portioned junction. The bi-portioned junction includes a doped outer portion and a doped inner portion. The dopant concentration of the outer portion is less than the dopant concentration of the inner portion. An electrical connection is formed by diffusion of the dopants within outer portion into a channel region and diffusion of the dopants within the outer portion into the inner region. A low contact resistance is achieved by a contact electrically contacting the relatively higher doped inner portion while device shorting is limited by the relatively lower doped outer portion.

Abstract translation: 诸如FinFET等的半导体结构包括双分支结。 双分支结包括掺杂的外部部分和掺杂的内部部分。 外部部分的掺杂剂浓度小于内部部分的掺杂剂浓度。 通过将外部部分内的掺杂剂扩散到沟道区域中并且将外部部分内的掺杂剂扩散到内部区域中而形成电连接。 低接触电阻通过电接触相对较高的掺杂内部部分的接触来实现，同时器件短路由相对较低的掺杂外部部分限制。