公开(公告)号：US20180267936A1

公开(公告)日：2018-09-20

申请号：US15460755

申请日：2017-03-16

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Jungwook Choi ,  Kailash Gopalakrishnan ,  Victor Han ,  Vijayalakshmi Srinivasan ,  Jintao Zhang

IPC: G06F17/16

CPC classification number: G06F17/16

Abstract: Techniques facilitating matrix multiplication on a systolic array are provided. A computer-implemented method can comprise populating, by a system operatively coupled to a processor, respective first registers of one or more processing elements of a systolic array structure with respective input data bits of a first data matrix. The one or more processing elements can comprise a first processing element that comprises a first input data bit of the first data matrix and a first activation bit of a second data matrix. The method can also include determining, by the system, at the first processing element, a first partial sum of a third data matrix. Further, the method can include streaming, by the system, the first partial sum of the third data matrix from the first processing element.

公开(公告)号：US09886640B1

公开(公告)日：2018-02-06

申请号：US15230934

申请日：2016-08-08

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Pierce I-Jen Chuang ,  Li-Wen Hung ,  Jui-Hsin Lai

IPC: G06K9/00 ,  G06K9/62 ,  G06F21/32

CPC classification number: G06K9/00906 ,  G06F21/32 ,  G06K9/00255 ,  G06K9/00288 ,  G06K9/2018

Abstract: A method, system and computer program product are disclosed that comprise capturing first image data of a person's face using at least one sensor responsive in a band of infrared wavelengths and capturing second image data of the person's face using the at least one sensor responsive in a band of visible wavelengths; extracting image features in the image data and detecting face regions; applying a similarity analysis to image feature edge maps extracted from the first and the second image data; and recognizing a presence of a live face image after regions found in the first image data pass a facial features classifier. Upon recognizing the presence of the live face image, additional operations can include verifying the identity of the person as an authorized person and granting the person access to a resource.

公开(公告)号：US09859281B2

公开(公告)日：2018-01-02

申请号：US15219894

申请日：2016-07-26

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Zuoguang Liu ,  Miaomiao Wang ,  Tenko Yamashita

IPC: H01L27/092 ,  H01L21/308 ,  H01L29/66 ,  H01L21/306 ,  H01L21/033 ,  H01L21/3065 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/04 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0922 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7855

Abstract: A technique for forming a semiconductor device is provided. Sacrificial mandrels are formed over a hardmask layer on a semiconductor layer. Spacers are formed on sidewalls of the sacrificial mandrels. The sacrificial mandrels are removed to leave the spacers. A masking process leaves exposed a first set of spacers with a second set protected. In response to the masking process, a first fin etch process forms a first set of fins in the semiconductor layer via first set of spacers. The first set of fins has a vertical sidewall profile. Another masking process leaves exposed the second set of spacers with the first set of spacers and the first set of fins protected. In response to the other masking process, a second fin etch process forms a second set of fins in semiconductor layer using the second set of spacers. The second set of fins has a trapezoidal sidewall profile.

公开(公告)号：US20170344558A1

公开(公告)日：2017-11-30

申请号：US15165144

申请日：2016-05-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chia-Yu Chen ,  Pei-Yun Hsueh ,  Jui-Hsin Lai ,  Yinglong Xia

IPC: G06F17/30

Abstract: A computer-implemented method, computer program product, and system for determination of critical parts and component correlations in a circuit using a correlation graph and centrality analysis including; receiving a circuit layout portion of a larger circuit layout, converting the circuit layout portion into a correlation graph representing components as nodes and connecting wires as edges, determining, using ground truth and Naïve Bayes to determine correlation weighting, scaling the correlation graph to represent the larger circuit, and presenting the larger correlation graph on a graphical user interface (GUI).

公开(公告)号：US20170288036A1

公开(公告)日：2017-10-05

申请号：US15629938

申请日：2017-06-22

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Zuoguang Liu ,  Sanjay C. Mehta ,  Tenko Yamashita

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/225 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8238 ,  H01L29/167 ,  H01L29/08 ,  H01L21/311 ,  H01L29/49 ,  H01L21/3065 ,  H01L29/45 ,  H01L21/285 ,  H01L29/40 ,  H01L23/485 ,  H01L29/417

CPC classification number: H01L29/456 ,  H01L21/225 ,  H01L21/2251 ,  H01L21/2252 ,  H01L21/2254 ,  H01L21/28518 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/495 ,  H01L29/516 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2.

公开(公告)号：US09741813B2

公开(公告)日：2017-08-22

申请号：US15248095

申请日：2016-08-26

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Zuoguang Liu ,  Sanjay C. Mehta ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L21/8238 ,  H01L29/45 ,  H01L21/768 ,  H01L21/225 ,  H01L29/78 ,  H01L29/417 ,  H01L29/51 ,  H01L21/3065 ,  H01L21/311 ,  H01L29/08 ,  H01L29/167 ,  H01L29/49 ,  H01L21/285 ,  H01L29/40 ,  H01L23/485

CPC classification number: H01L29/456 ,  H01L21/225 ,  H01L21/2251 ,  H01L21/2252 ,  H01L21/2254 ,  H01L21/28518 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/495 ,  H01L29/516 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2.

公开(公告)号：US20170219519A1

公开(公告)日：2017-08-03

申请号：US15014350

申请日：2016-02-03

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Shu-Jen Han

IPC: G01N27/414

CPC classification number: G01R27/02 ,  G01N27/02 ,  G01N27/4148 ,  G01N33/0031

Abstract: Frequency division multiplexing-based techniques for FET-based sensor arrays are provided. In one aspect, a sensor device includes: an array of FET-based sensors, wherein the sensors are grouped into multiple channels, and wherein each of the sensors includes an insulator on a substrate, a local gate embedded in the insulator, a channel material over the local embedded gate, and source and drain electrodes in contact with opposite ends of the channel material, and wherein a surface of the channel material is functionalized to react with at least one target molecule. The sensors in a given channel can be modulated (via the local gate) to enable the signal read out from the channel to be divided in the frequency domain based on the different frequencies used to modulate the sensors.

公开(公告)号：US09391152B1

公开(公告)日：2016-07-12

申请号：US14600077

申请日：2015-01-20

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/45 ,  H01L29/78 ,  H01L29/417 ,  H01L21/285 ,  H01L21/311 ,  H01L21/265 ,  H01L21/02 ,  H01L21/321

CPC classification number: H01L29/49 ,  H01L21/02244 ,  H01L21/02255 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/285 ,  H01L21/28568 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/76814 ,  H01L21/76831 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a metal-insulator-semiconductor (MIS) contact, a transistor including the MIS contact, and the MIS contact are described. The method includes etching an opening for formation of the contact, the opening extending to an upper surface of a semiconductor region. The method also includes implanting metal ions at a selected depth within the upper surface of the semiconductor region and converting the upper surface of the semiconductor region to a metal oxide insulating layer. The method further includes forming a metal layer on the insulating layer.

Abstract translation: 描述了形成金属 - 绝缘体半导体（MIS）接触的方法，包括MIS接触的晶体管和MIS接触。 该方法包括蚀刻用于形成接触的开口，该开口延伸到半导体区域的上表面。 该方法还包括在半导体区域的上表面内的选定深度处注入金属离子，并将半导体区域的上表面转换为金属氧化物绝缘层。 该方法还包括在绝缘层上形成金属层。

公开(公告)号：US12261619B2

公开(公告)日：2025-03-25

申请号：US18085094

申请日：2022-12-20

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Ankur Agrawal ,  Andrea Fasoli ,  Kyu-hyoun Kim

IPC: H03M1/38

Abstract: An apparatus includes multiple analog to digital converters. Individual analog to digital converters are configured to produce a digital output from an analog input and configured to compute a least significant bit of the digital output by comparing an internal residual voltage for determination of the least significant bit and a residual voltage from another analog to digital converter.

公开(公告)号：US12141513B2

公开(公告)日：2024-11-12

申请号：US16177017

申请日：2018-10-31

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Jungwook Choi ,  Kailash Gopalakrishnan ,  Vijayalakshmi Srinivasan ,  Swagath Venkataramani ,  Jintao Zhang

IPC: G06F30/3323 ,  G06F111/04 ,  G06N3/04 ,  G06N3/063

Abstract: A method for improving performance of a predefined Deep Neural Network (DNN) convolution processing on a computing device includes inputting parameters, as input data into a processor on a computer that formalizes a design space exploration of a convolution mapping, on a predefined computer architecture that will execute the predefined convolution processing. The parameters are predefined as guided by a specification for the predefined convolution processing to be implemented by the convolution mapping and by a microarchitectural specification for the processor that will execute the predefined convolution processing. The processor calculates performance metrics for executing the predefined convolution processing on the computing device, as functions of the predefined parameters, as proxy estimates of performance of different possible design choices to implement the predefined convolution processing.