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公开(公告)号：US20200014058A1
公开(公告)日：2020-01-09
申请号：US16026448
申请日：2018-07-03
IPC分类号： H01M10/0525 , H01M10/0562 , H01M4/485 , H01M4/134 , H01M4/66 , H01M2/16 , H02J7/00 , B60L11/18
摘要： Rechargeable lithium-ion batteries that have a high-capacity and a fast charge rate are provided. The lithium-ion batteries contain an anode structure that is of unitary construction and includes a non-porous region and a porous region including a top porous layer (Porous Region 1) having a first thickness and a first porosity, and a bottom porous layer (Porous Region 2) located beneath the top porous layer and forming an interface with the non-porous region. At least an upper portion of the non-porous region and the entirety of the porous region are composed of silicon, and the bottom porous layer has a second thickness that is greater than the first thickness, and a second porosity that is greater than the first porosity.
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公开(公告)号：US20200014018A1
公开(公告)日：2020-01-09
申请号：US16026426
申请日：2018-07-03
发明人： Joel P. de Souza , John Collins , Devendra K. Sadana , John A. Ott , Marinus J. P. Hopstaken , Stephen W. Bedell
IPC分类号： H01M4/04 , H01M10/0525 , H01M10/0567 , H01M10/0562 , H01M4/134 , H01M4/66 , H01M4/1395 , H01M4/485
摘要： An anode structure for rechargeable lithium-ion batteries that have a high-capacity are provided. The anode structure, which is made utilizing an anodic etching process, is of unitary construction and includes a non-porous region and a porous region including a top porous layer (Porous Region 1) having a first thickness and a first porosity, and a bottom porous layer (Porous Region 2) located beneath the top porous layer and forming an interface with the non-porous region. At least an upper portion of the non-porous region and the entirety of the porous region are composed of silicon, and the bottom porous layer has a second thickness that is greater than the first thickness, and a second porosity that is greater than the first porosity.
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公开(公告)号：US20190103637A1
公开(公告)日：2019-04-04
申请号：US15721061
申请日：2017-09-29
IPC分类号： H01M10/0585 , H01M4/04
摘要： Methods of forming high-capacity and high-performance rechargeable batteries are provided by forming a rechargeable battery stack that includes a spalled material structure that includes a spalled cathode material that is attached to a stressor material. The spalled cathode material may include a single crystalline or polycrystalline cathode material that is devoid of polymeric binders. The stressor material serves as a cathode current collector of the rechargeable battery stack.
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公开(公告)号：US20190035923A1
公开(公告)日：2019-01-31
申请号：US15663133
申请日：2017-07-28
发明人： Devendra Sadana , Dechao Guo , Joel P. de Souza , Ruqiang Bao , Stephen W. Bedell , Shogo Mochizuki , Gen Tsutsui , Hemanth Jagannathan , Marinus Hopstaken
IPC分类号： H01L29/78 , H01L29/66 , H01L21/762 , H01L21/02 , H01L29/161 , H01L29/04
CPC分类号： H01L29/785 , H01L21/02123 , H01L21/02304 , H01L21/0245 , H01L21/02516 , H01L21/02532 , H01L21/0262 , H01L21/762 , H01L29/04 , H01L29/045 , H01L29/1054 , H01L29/161 , H01L29/517 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66666
摘要： Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.
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公开(公告)号：US10157993B2
公开(公告)日：2018-12-18
申请号：US15183336
申请日：2016-06-15
IPC分类号： H01L29/66 , H01L21/265 , H01L21/28 , H01L29/08 , H01L29/267 , H01L29/43
摘要： A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. An n-type material is formed on or in the p-doped layer. The n-type layer includes ZnO. An aluminum contact is formed in direct contact with the ZnO of the n-type material to form an electronic device.
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公开(公告)号：US10103111B2
公开(公告)日：2018-10-16
申请号：US15390654
申请日：2016-12-26
发明人： Ali Afzali-Ardakani , Joel P. de Souza , Bahman Hekmatshoartabari , Daniel M. Kuchta , Devendra K. Sadana
IPC分类号： H01L29/04 , H01L23/00 , H01L31/0203 , H01L31/02 , H01L31/112 , H01L31/024 , H01L31/14 , H01L31/0376 , H01L31/0216 , H01L31/20
摘要： Silicon-based or other electronic circuitry is dissolved or otherwise disabled by reactive materials within a semiconductor chip should the chip or a device containing the chip be subjected to tampering. Triggering circuits containing normally-OFF heterojunction field-effect photo-transistors are configured to cause reactions of the reactive materials within the chips upon exposure to light. The normally-OFF heterojunction field-effect photo-transistors can be fabricated during back-end-of-line processing through the use of polysilicon channel material, amorphous hydrogenated silicon gate contacts, hydrogenated crystalline silicon source/drain contacts, or other materials that allow processing at low temperatures.
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公开(公告)号：US10079341B1
公开(公告)日：2018-09-18
申请号：US15457433
申请日：2017-03-13
发明人： Stephen W. Bedell , Kevin W. Brew , Joel P. de Souza , Seyoung Kim , Ning Li , Yun Seog Lee , Devendra K. Sadana
摘要： A three-terminal non-volatile multi-state device based on mobile ion induced electrical resistivity change is provided. The three-terminal non-volatile multi-state memory device includes a substrate having a first electrode and a second electrode therein. The three-terminal non-volatile multi-state memory device further includes a mobile ion including resistor layer disposed over the first electrode, the second electrode, and part of the substrate. The three-terminal non-volatile multi-state memory device also includes a third electrode formed over the mobile ion including resistor layer. The three-terminal non-volatile multi-state memory device provides multi-level states determined by an electrical resistivity the mobile ion including resistor layer which changes the electrical resistivity based on the mobile ion concentration in the material.
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公开(公告)号：US20180261764A1
公开(公告)日：2018-09-13
申请号：US15457433
申请日：2017-03-13
发明人： Stephen W. Bedell , Kevin W. Brew , Joel P. de Souza , Seyoung Kim , Ning Li , Yun Seog Lee , Devendra K. Sadana
摘要： A three-terminal non-volatile multi-state memory device based on mobile ion induced electrical resistivity change is provided. The three-terminal non-volatile multi-state memory device-includes a substrate having a first electrode and a second electrode therein. The three-terminal non-volatile multi-state memory device further includes a mobile ion including resistor layer disposed over the first electrode, the second electrode, and part of the substrate. The three-terminal non-volatile multi-state memory device also includes a third electrode formed over the mobile ion including resistor layer. The three-terminal non-volatile multi-state memory device provides multi-level states determined by an electrical resistivity of the mobile ion including resistor layer which changes the electrical resistivity based on the mobile ton concentration in the material.
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公开(公告)号：US10038057B2
公开(公告)日：2018-07-31
申请号：US15450649
申请日：2017-03-06
IPC分类号： H01L29/68 , H01L29/43 , H01L29/08 , H01L29/267 , H01L29/78 , H01L29/66 , H01L29/868 , H01L29/861 , H01L29/06
CPC分类号： H01L29/0847 , H01L29/0649 , H01L29/0895 , H01L29/267 , H01L29/66219 , H01L29/66522 , H01L29/66613 , H01L29/66643 , H01L29/66969 , H01L29/78 , H01L29/861 , H01L29/868
摘要： A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. A dielectric interlayer is formed on the p-doped layer. An n-type layer is formed on the dielectric interlayer, the n-type layer including a high band gap II-VI material to form an electronic device.
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公开(公告)号：US20180197805A1
公开(公告)日：2018-07-12
申请号：US15815997
申请日：2017-11-17
CPC分类号： H01L23/3171 , H01L21/0206 , H01L21/02112 , H01L21/02227 , H01L21/02359 , H01L21/02362 , H01L23/29 , H01L23/291 , H01L23/298 , H01L23/3135 , H01L23/3192 , H01L29/20 , H01L29/408 , H01L29/513 , H01L29/517
摘要： Embodiments are directed to a method of passivating a surface of a high-mobility semiconductor and resulting structures having a reduced interface defect density. A semiconductor layer is formed on a substrate. A surface of the semiconductor layer is contacted with a sulfur source including thiourea at a temperature of up to about 90 degrees Celsius to form a sulfur passivation layer on the surface of the semiconductor layer. A dielectric layer is formed on the sulfur passivation layer and a minimum of interface trap density distribution at an interface between the semiconductor layer and the dielectric layer is less than about 2.0×1011 cm−2eV−1.
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