公开(公告)号：US06975133B1

公开(公告)日：2005-12-13

申请号：US10709784

申请日：2004-05-27

申请人： Victor Wing Chung Chan ,  Hsing-Jen C. Wann ,  Shih-Fen Huang ,  Oleg Gluschenkov

发明人： Victor Wing Chung Chan ,  Hsing-Jen C. Wann ,  Shih-Fen Huang ,  Oleg Gluschenkov

IPC分类号： H01L27/02 ,  H03K17/16 ,  H03K19/017 ,  H03K19/094 ,  H03K19/0948

CPC分类号： H03K19/0948 ,  H01L27/0203 ,  H03K19/01707

摘要： A logic circuit is provided with a first inverter having a plurality of linear gate transistors driving a first capacitive load and a second inverter having a plurality of cellular gate transistors driving a second capacitive load. The first inverter is serially connected to the second inverter. The second capacitive load is larger than the first capacitive load.

摘要翻译： 逻辑电路设置有具有驱动第一电容性负载的多个线性栅极晶体管的第一反相器和驱动第二电容负载的多个蜂窝状栅极晶体管的第二反相器。 第一个逆变器串联连接到第二个逆变器。 第二容性负载大于第一容性负载。

公开(公告)号：US20050260808A1

公开(公告)日：2005-11-24

申请号：US10851830

申请日：2004-05-21

申请人： Xiangdong Chen ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Brian Greene ,  Kern Rim ,  Haining Yang

发明人： Xiangdong Chen ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Brian Greene ,  Kern Rim ,  Haining Yang

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a semiconducting device including at least one gate region including a gate conductor located on a surface of a substrate, the substrate having an exposed surface adjacent the gate region; a silicide contact located adjacent the exposed surface; and a stress inducing liner located on the silicide contact, the exposed surface of the substrate adjacent to the gate region and the at least one gate region, wherein the stress inducing liner provides a stress to a device channel portion of the substrate underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 200 MPa to about 2000 MPa. The present invention also provides a method for forming the above-described semiconducting device.

摘要翻译： 本发明提供了一种半导体器件，其包括至少一个栅极区域，该栅极区域包括位于衬底表面上的栅极导体，该衬底具有邻近栅极区域的暴露表面; 位于暴露表面附近的硅化物触点; 以及位于所述硅化物接触处的所述应力诱导衬垫，所述衬底的与所述栅极区域和所述至少一个栅极区域相邻的暴露表面，其中所述应力诱导衬垫向所述栅极区域下方的衬底的器件沟道部分施加应力 。 在器件通道上产生的应力是约200MPa至约2000MPa的纵向应力。 本发明还提供了形成上述半导体器件的方法。

公开(公告)号：US20050194699A1

公开(公告)日：2005-09-08

申请号：US10708430

申请日：2004-03-03

申请人： Michael Belyansky ,  Bruce Doris ,  Oleg Gluschenkov

发明人： Michael Belyansky ,  Bruce Doris ,  Oleg Gluschenkov

IPC分类号： H01L27/088

CPC分类号： H01L29/0653 ,  H01L29/66636 ,  H01L29/7848

摘要： Compressive or tensile materials are selectively introduced beneath and in alignment with spacer areas and adjacent to channel areas of a semiconductor substrate to enhance or degrade electron and hole mobility in CMOS circuits. A process entails steps of creating dummy spacers, forming a dielectric mandrel (i.e., mask), removing the dummy spacers, etching recesses into the underlying semiconductor substrate, introducing a compressive or tensile material into a portion of each recess, and filling the remainder of each recess with substrate material.

摘要翻译： 压缩或拉伸材料被选择性地引入到间隔区域的下方并且与半导体衬底的通道区域相邻并且与CMOS电路中的电子和空穴迁移率相关联。 一个过程需要创建虚拟间隔物的步骤，形成介质心轴（即掩模），去除虚拟间隔物，将凹槽蚀刻到下面的半导体衬底中，将压缩或拉伸材料引入每个凹部的一部分中， 每个凹槽与基底材料。

公开(公告)号：US06930060B2

公开(公告)日：2005-08-16

申请号：US10250257

申请日：2003-06-18

申请人： Anthony I. Chou ,  Michael P. Chudzik ,  Toshiharu Furukawa ,  Oleg Gluschenkov ,  Paul D. Kirsch ,  Kristen C. Scheer ,  Joseph Shepard, Jr.

发明人： Anthony I. Chou ,  Michael P. Chudzik ,  Toshiharu Furukawa ,  Oleg Gluschenkov ,  Paul D. Kirsch ,  Kristen C. Scheer ,  Joseph Shepard, Jr.

IPC分类号： H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L29/51 ,  H01L21/31 ,  H01L29/76

CPC分类号： H01L21/0228 ,  H01L21/0214 ,  H01L21/02148 ,  H01L21/02205 ,  H01L21/02211 ,  H01L21/02299 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28282 ,  H01L21/3144 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/518

摘要： Methods for preparing a silicon oxynitride layer where the silicon oxynitride layer is deposited atop a substrate and have a low concentration of nitrogen at the interface of the silicon oxynitride layer and the substrate. The silicon oxynitride layer is formed by pulsing at least one interface precursor onto a substrate, where said substrate chemisorbs a portion of said at least one interface precursor to form a monolayer of said at least one interface precursor; and pulsing a nitrogen-containing precursor onto said substrate containing said monolayer of interface precursor, where said monolayer of said at least one interface precursor chemisorbs a portion of said nitrogen-containing precursor to form a monolayer of said nitrogen-containing precursor. The interface precursor includes oxygen-containing or silicon-containing precursor gasses.

摘要翻译： 制备氮氧化硅层的方法，其中氧氮化硅层沉积在基板顶部并且在氮氧化硅层和基板的界面处具有低浓度的氮。 通过将至少一种界面前体脉冲至基底上形成氧氮化硅层，其中所述基底化学吸附所述至少一种界面前体的一部分以形成所述至少一种界面前体的单层; 并且将含氮前体脉冲至含有所述界面前体单层的所述基质上，其中所述至少一种界面前体的所述单层化学吸附所述含氮前体的一部分以形成所述含氮前体的单层。 界面前体包括含氧或含硅的前体气体。

公开(公告)号：US20050158931A1

公开(公告)日：2005-07-21

申请号：US11081271

申请日：2005-03-16

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  An Steegen ,  Haining Yang

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  An Steegen ,  Haining Yang

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L21/337

CPC分类号： H01L21/84 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions of only the PFET and not of the NFET. A process of making the PFET and NFET is provided. Trenches are etched in the areas to become the source and drain regions of the PFET and a lattice-mismatched silicon germanium layer is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon can be grown over the silicon germanium layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.

摘要翻译： 提供集成电路的p型场效应晶体管（PFET）和n型场效应晶体管（NFET）。 第一应变施加到PFET的沟道区，而不是NFET通过位于仅仅PFET而不是NFET的源极和漏极区域中的晶格不匹配的半导体层，例如硅锗。 提供制造PFET和NFET的工艺。 在区域中蚀刻沟槽以成为PFET的源极和漏极区域，并且将晶格失配的硅锗层外延生长以向与其相邻的PFET的沟道区域施加应变。 可以在硅锗层上生长一层硅层，并从硅层形成硅化物以提供低电阻源极和漏极区域。

公开(公告)号：US20050158924A1

公开(公告)日：2005-07-21

申请号：US10707878

申请日：2004-01-20

申请人： Ashima Chakravarti ,  Bruce Doris ,  Romany Ghali ,  Oleg Gluschenkov ,  Michael Gribelyuk ,  Woo-Hyeong Lee ,  Anita Madan

发明人： Ashima Chakravarti ,  Bruce Doris ,  Romany Ghali ,  Oleg Gluschenkov ,  Michael Gribelyuk ,  Woo-Hyeong Lee ,  Anita Madan

IPC分类号： C23C16/24 ,  C23C16/46 ,  H01L21/00 ,  H01L21/205 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC分类号： C23C16/24 ,  C23C16/46 ,  H01L21/28035 ,  H01L21/32055 ,  H01L29/4925

摘要： A method of forming polycrystalline silicon with ultra-small grain sizes employs a differential heating of the upper and lower sides of the substrate of a CVD apparatus, in which the lower side of the substrate receives considerably more power than the upper side, preferable more than 75% of the power; and in which the substrate is maintained during deposition at a temperature more than 50° C. above the 550° C. crystallization temperature of silicon.

摘要翻译： 形成超小晶粒尺寸的多晶硅的方法采用CVD装置的衬底的上侧和下侧的差分加热，其中衬底的下侧比上侧受到明显更多的功率，优选大于 75％的权力; 并且其中在超过550℃的硅结晶温度超过50℃的温度下在沉积期间保持基底。

公开(公告)号：US20050093059A1

公开(公告)日：2005-05-05

申请号：US10695752

申请日：2003-10-30

申请人： Michael Belyansky ,  Dureseti Chidambarrao ,  Omer Dokumaci ,  Bruce Deris ,  Oleg Gluschenkov

发明人： Michael Belyansky ,  Dureseti Chidambarrao ,  Omer Dokumaci ,  Bruce Deris ,  Oleg Gluschenkov

IPC分类号： H01L21/20 ,  H01L21/28 ,  H01L21/302 ,  H01L21/336 ,  H01L21/44 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/72 ,  H01L29/78 ,  H01L29/786 ,  H01L31/062

CPC分类号： H01L29/7845 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/785

摘要： In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nFET and PFET), carrier mobility is enhanced or otherwise regulated through the reacting the material of the gate electrode with a metal to produce a stressed alloy (preferably CoSi2, NiSi, or PdSi) within a transistor gate. In the case of both the nFET and pFET, the inherent stress of the respective alloy results in an opposite stress on the channel of respective transistor. By maintaining opposite stresses in the nFET and pFET alloys or silicides, both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.

摘要翻译： 在制造包括nFET和PFET的互补金属氧化物半导体（CMOS）场效应晶体管的情况下，通过使栅电极的材料与金属反应来增强或调节载流子迁移率，以产生应力合金（优选CoSi 2Si，NiSi或PdSi）。 在nFET和pFET两者的情况下，各合金的固有应力对相应晶体管的沟道产生相反的应力。 通过在nFET和pFET合金或硅化物中保持相反的应力，单个芯片或衬底上的两种类型的晶体管可以实现增强的载流子迁移率，从而提高CMOS器件和集成电路的性能。

公开(公告)号：US20050087824A1

公开(公告)日：2005-04-28

申请号：US10605769

申请日：2003-10-24

申请人： Cyril Cabral ,  Omer Dokumaci ,  Oleg Gluschenkov

发明人： Cyril Cabral ,  Omer Dokumaci ,  Oleg Gluschenkov

IPC分类号： G05F1/10 ,  G05F3/02 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/51 ,  H01L29/76 ,  H01L29/772 ,  H01L29/78 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/28194 ,  H01L21/28202 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7836

摘要： field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETs. The FETs have a device channel and a gate above the device channel with a doped source/drain extension at said each end of the thin channel. A portion of a low resistance material layer (e.g., a silicide layer) is disposed on source/drain extensions. The portions on the doped extensions laterally form a direct contact with the doped source/drain extension. Any low resistance material layer on the gate is separated from the low resistance material portions on the source/drain extensions.

摘要翻译： 场效应晶体管（FET），包括FET的集成电路（IC）芯片和形成FET的方法。 FET在器件沟道上方具有器件沟道和栅极，在薄沟道的每个端部具有掺杂的源极/漏极延伸。 低电阻材料层（例如硅化物层）的一部分设置在源极/漏极延伸部分上。 掺杂延伸部分上的部分横向形成与掺杂源极/漏极延伸部的直接接触。 栅极上的任何低电阻材料层与源极/漏极延伸部分上的低电阻材料部分分离。

公开(公告)号：US20050059214A1

公开(公告)日：2005-03-17

申请号：US10605227

申请日：2003-09-16

申请人： Kangguo Cheng ,  Dureseti Chidambarrao ,  Rama Divakaruni ,  Oleg Gluschenkov

发明人： Kangguo Cheng ,  Dureseti Chidambarrao ,  Rama Divakaruni ,  Oleg Gluschenkov

IPC分类号： H01L21/8242 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L27/10864 ,  H01L27/10867 ,  H01L27/10876 ,  H01L27/10888

摘要： A trench capacitor vertical-transistor DRAM cell in a SiGe wafer compensates for overhang of the pad nitride by forming an epitaxial strained silicon layer on the trench walls that improves transistor mobility, removes voids from the poly trench fill and reduces resistance on the bitline contact.

摘要翻译： SiGe晶片中的沟槽电容器垂直晶体管DRAM单元通过在沟槽壁上形成外延应变硅层来补偿衬垫氮化物的突出，从而提高晶体管的迁移率，从多沟槽填充中去除空隙并降低位线接触的电阻。

公开(公告)号：US06727142B1

公开(公告)日：2004-04-27

申请号：US10284508

申请日：2002-10-29

申请人： Oleg Gluschenkov ,  Suryanarayan G. Hegde ,  Helmut H. Tews

发明人： Oleg Gluschenkov ,  Suryanarayan G. Hegde ,  Helmut H. Tews

IPC分类号： H01L2126

CPC分类号： H01L21/02332 ,  H01L21/02247 ,  H01L21/3141 ,  H01L21/3144 ,  H01L21/32105

摘要： Forming a vertical MOS transistor or making another three-dimensional integrated circuit structure in a silicon wafer exposes planes having at least two different crystallographic orientations. Growing oxide on different crystal planes is inherently at different growth rates because the inter-atomic spacing is different in the different planes. Heating the silicon in a nitrogen-containing ambient to form a thin layer of nitride and then growing the oxide through the thin nitrided layer reduces the difference in oxide thickness to less than 1%.

摘要翻译： 形成垂直MOS晶体管或在硅晶片中制造另一三维集成电路结构暴露具有至少两个不同晶体取向的平面。 不同晶面上生长的氧化物固有地在不同的生长速率下，因为不同平面中原子间的间距是不同的。 在含氮环境中加热硅以形成氮化物薄层，然后通过薄氮化层生长氧化物，将氧化物厚度的差异减小到小于1％。