Adhesive-bonded substrates in a multi-chip module
    72.
    发明授权
    Adhesive-bonded substrates in a multi-chip module 有权
    多芯片模块中的粘合粘合基板

    公开(公告)号:US08698322B2

    公开(公告)日:2014-04-15

    申请号:US12730823

    申请日:2010-03-24

    IPC分类号: H01L23/538

    摘要: A multi-chip module (MCM) is described in which at least two substrates are mechanically coupled by an adhesive layer that maintains alignment and a zero (or near zero) spacing between proximity connectors on surfaces of the substrates, thereby facilitating high signal quality during proximity communication between the substrates. In order to provide sufficient shear strength, the adhesive layer has a thickness that is larger than the spacing. This may be accomplished using one or more positive and/or negative features on the substrates. For example, the adhesive may be bonded to: one of the surfaces and an inner surface of a channel that is recessed below the other surface; inner surfaces of channels that are recessed below both of the surfaces; or both of the surfaces. In this last case, the zero (or near zero) spacing may be achieved by disposing proximity connectors on a mesa that protrudes above at least one of the substrate surfaces.

    摘要翻译: 描述了一种多芯片模块(MCM),其中至少两个基板通过粘合剂层机械耦合,所述粘合剂层在基板的表面上的接近连接器之间保持对准和零(或接近零)的间隔,从而有利于高信号质量 基板之间的接近连接。 为了提供足够的剪切强度,粘合剂层的厚度大于间隔。 这可以使用衬底上的一个或多个正和/或负特征来实现。 例如,粘合剂可以结合到:一个表面和在另一个表面下方凹进的通道的内表面; 在两个表面下凹陷的通道的内表面; 或两个表面。 在最后一种情况下,零(或接近零)的间距可以通过将接近连接器设置在突出在至少一个衬底表面上的台面上来实现。

    SYNCHRONIZER LATCH CIRCUIT THAT FACILITATES RESOLVING METASTABILITY
    73.
    发明申请
    SYNCHRONIZER LATCH CIRCUIT THAT FACILITATES RESOLVING METASTABILITY 有权
    同步化电路可以解决易变性

    公开(公告)号:US20130135017A1

    公开(公告)日:2013-05-30

    申请号:US13306828

    申请日:2011-11-29

    IPC分类号: H03L7/06 H03L7/00

    CPC分类号: H03K3/356173 H03K3/0375

    摘要: The disclosed embodiments provide a synchronizer latch circuit that facilitates resolving metastability issues. This synchronizer latch circuit includes a set of lightly loaded, cross-coupled transistors that form a metastable resolving and state-holding element that is coupled to two outputs. An incoming synchronization signal creates a voltage difference between the two outputs, but does not directly force a state change for the outputs. Instead, the data and clock inputs control transistors that allow neighboring power sources and/or ground network connections to weakly influence the outputs. The cross-coupled transistors then amplify the resulting voltage difference to generate valid output voltages, even when the data input and clock signal are received at roughly the same time. Thus, the synchronizer latch circuit facilitates rapidly resolving metastability and improving synchronizer performance.

    摘要翻译: 所公开的实施例提供了一种有助于解决亚稳态问题的同步器锁存电路。 该同步器锁存电路包括一组轻负载的交叉耦合晶体管,其形成耦合到两个输出的亚稳分解和状态保持元件。 输入同步信号在两个输出之间产生电压差,但不会直接强制输出的状态变化。 相反,数据和时钟输入控制晶体管,允许相邻的电源和/或地面网络连接弱影响输出。 交叉耦合晶体管然后放大所产生的电压差以产生有效的输出电压,即使在大致相同的时间接收数据输入和时钟信号。 因此,同步器锁存电路有助于快速分辨亚稳态并提高同步器性能。

    Method for manufacturing an active socket for facilitating proximity communication
    75.
    发明授权
    Method for manufacturing an active socket for facilitating proximity communication 有权
    用于制造用于促进邻近通信的有源插座的方法

    公开(公告)号:US08166644B2

    公开(公告)日:2012-05-01

    申请号:US12498282

    申请日:2009-07-06

    IPC分类号: H05K3/30

    摘要: One embodiment of the present invention provides a system that facilitates capacitive communication between integrated circuit chips. The system includes a substrate having an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. The system additionally includes an integrated circuit chip having an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. Additionally, the integrated circuit chip is pressed against the substrate such that the active face of the integrated circuit chip is parallel to and adjacent to the active face of the substrate, and capacitive signal pads on the active face of the integrated circuit chip overlap signal pads on the active face of the substrate. The arrangement of the substrate and integrated circuit chip facilitates communication between the integrated circuit chip and the substrate through capacitive coupling via the overlapping signal pads.

    摘要翻译: 本发明的一个实施例提供一种促进集成电路芯片之间的电容性通信的系统。 该系统包括具有活动面的衬底,有源电路和信号垫位于该衬底上,以及与主动面相对的背面。 该系统还包括集成电路芯片,其具有有源电路和信号焊盘所在的有源面以及与有源面相对的背面。 此外,集成电路芯片被压靠在基板上,使得集成电路芯片的有源面平行于并邻近衬底的有源面,并且集成电路芯片的有源面上的电容性信号焊盘与信号焊盘重叠 在基板的主动面上。 衬底和集成电路芯片的布置通过经由重叠的信号焊盘的电容耦合便于集成电路芯片和衬底之间的通信。

    OPTICAL CONNECTOR WITH REDUCED MECHANICAL-ALIGNMENT SENSITIVITY
    77.
    发明申请
    OPTICAL CONNECTOR WITH REDUCED MECHANICAL-ALIGNMENT SENSITIVITY 有权
    具有降低机械对准灵敏度的光学连接器

    公开(公告)号:US20100329607A1

    公开(公告)日:2010-12-30

    申请号:US12495228

    申请日:2009-06-30

    IPC分类号: G02B6/34 G02B6/26

    摘要: An optical connector is described. This optical connector spatially segregates optical coupling between an optical fiber and an optical component, which relaxes the associated mechanical-alignment requirements. In particular, the optical connector includes an optical spreader component disposed on a substrate. This optical spreader component is optically coupled to the optical fiber at a first coupling region, and is configured to optically couple to the optical component at a second coupling region that is at a different location on the substrate than the first coupling region. Moreover, the first coupling region and the second coupling region are optically coupled by an optical waveguide.

    摘要翻译: 描述光连接器。 该光学连接器在空间上分离光纤和光学部件之间的光学耦合,这松弛了相关的机械对准要求。 特别地,光连接器包括设置在基板上的光扩散部件。 该光扩散器部件在第一耦合区域光学耦合到光纤,并且被配置为在与第一耦合区域在基板上的不同位置处的第二耦合区域光学耦合到光学部件。 此外,第一耦合区域和第二耦合区域通过光波导光学耦合。

    PROTECTION FOR PROXIMITY ELECTRONICS AGAINST ELECTROSTATIC DISCHARGE
    78.
    发明申请
    PROTECTION FOR PROXIMITY ELECTRONICS AGAINST ELECTROSTATIC DISCHARGE 有权
    针对静电放电的接近电子保护

    公开(公告)号:US20090315157A1

    公开(公告)日:2009-12-24

    申请号:US12144142

    申请日:2008-06-23

    IPC分类号: H01L23/62

    摘要: A system of protecting a proximity communication system against electrostatic discharge (ESD). The proximity communication system includes two chips, each having an array of electrical pads at its surface and covered by a thin dielectric layer such that capacitive coupling circuits are formed between the chips when they are joined together. In at least one of the chips, an additional protection pad is formed away from the array, and heavy protection circuitry is connected to it. Its surface is exposed through the dielectric surface over it such that, when an ESD aggressor approaches, the discharge occurs to the protection pad.

    摘要翻译: 保护接近通信系统免受静电放电(ESD)的系统。 接近通信系统包括两个芯片,每个芯片在其表面上具有电焊盘的阵列并被薄的电介质层覆盖,使得当它们连接在一起时,在芯片之间形成电容耦合电路。 在至少一个芯片中,附加的保护焊盘远离阵列形成,重保护电路与其连接。 其表面通过其上的电介质表面暴露,使得当ESD侵蚀器接近时,放电发生到保护焊盘。

    DIVERSITY PROXIMITY COMMUNICATION
    79.
    发明申请
    DIVERSITY PROXIMITY COMMUNICATION 有权
    多样性接近通信

    公开(公告)号:US20090279571A1

    公开(公告)日:2009-11-12

    申请号:US12115772

    申请日:2008-05-06

    摘要: A diversity proximity communication system formed on two juxtaposed chips, one having a two-dimensional array of transmit elements, the other having a two-dimensional array of receive elements. The receive and transmit elements need not be aligned and may have nominal alignment of one transmit element overlapping the corners of four receive elements. The elements may be electrical pads capacitively coupled across the interface. Signals of four different multiplexing groups, e.g., time-multiplexed, are supplied to transmitting elements in a 2×2 array. Signals from four receive elements in a 2×2 array are amplified, combined, and demultiplexed for the selected multiplexing group. The gains for the four signals to be combined are differentially controlled to increase the signal-to-noise ratio. The amplification may be determined by the overlap between each of the receive elements and the transmit element of the selected multiplexing group.

    摘要翻译: 在两个并置芯片上形成的分集接近通信系统,一个具有发射元件的二维阵列,另一个具有接收元件的二维阵列。 接收和发送元件不需要对齐,并且可以具有与四个接收元件的角重叠的一个发射元件的标称对准。 元件可以是跨接口电容耦合的电焊盘。 四个不同复用组的信号,例如时分复用,被提供给2x2阵列中的发射元件。 来自2x2阵列中的四个接收元件的信号被放大,组合和解复用用于所选择的复用组。 要组合的四个信号的增益被差分控制以增加信噪比。 可以通过每个接收元件与所选多路复用组的发送元件之间的重叠来确定放大。

    Method and apparatus for electronically aligning capacitively coupled mini-bars
    80.
    发明授权
    Method and apparatus for electronically aligning capacitively coupled mini-bars 有权
    用于电容对齐电容耦合迷你条的方法和装置

    公开(公告)号:US07384804B2

    公开(公告)日:2008-06-10

    申请号:US11125792

    申请日:2005-05-09

    IPC分类号: H01L21/66

    摘要: One embodiment of the present invention provides a system that electronically aligns mini-bars on different semiconductor chips which are situated face-to-face to facilitate communication between the semiconductor chips through capacitive coupling. During operation, the system measures an alignment between a first chip and a second chip. The system then selects a group of transmitter mini-bars on the first chip to form a transmitter bit position based on the measured alignment. In this way, the system allows a data signal to be distributed to and transmitted by the mini-bars that form the transmitter bit position. The system also selects a group of receiver mini-bars on the second chip to form a receiver bit position based on the measured alignment. Next, the system associates transmitter bit positions on the first chip with proximate receiver bit positions on the second chip based on the measured alignment. In this way, the system allows data signals transmitted by the mini-bars within a transmitter bit position on the first chip to be collectively received by the mini-bars within an associated receiver bit position on the second chip.

    摘要翻译: 本发明的一个实施例提供了一种系统,其电子地对准位于面对面的不同半导体芯片上的迷你条,以促进半导体芯片之间通过电容耦合的通信。 在操作期间,系统测量第一芯片和第二芯片之间的对准。 然后,系统在第一芯片上选择一组发射器迷你条,以基于测量的对准来形成发射机位置。 以这种方式,该系统允许将数据信号分配到形成发送器位位置的迷你条并发送。 该系统还在第二芯片上选择一组接收器迷你条,以形成基于测量对准的接收器位位置。 接下来,系统基于测量的对准将第一芯片上的发射机位位置与第二芯片上的接收器位置相关联。 以这种方式,系统允许由第一芯片上的发送器位置内的迷你条发送的数据信号由第二芯片上相关联的接收器位位置内的迷你条集中接收。