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公开(公告)号：US09859819B2
公开(公告)日：2018-01-02
申请号：US14745696
申请日：2015-06-22
Inventor： Yi Heng Tsai , Chia-Hua Chu , Kuei-Sung Chang
IPC: H02N1/00 , G01P15/125 , B81B3/00 , G01P15/08
CPC classification number: H02N1/006 , B81B3/0005 , B81B3/0008 , B81B3/001 , B81B2201/0235 , G01P15/125 , G01P2015/0871 , H02N1/00 , Y10T29/49002
Abstract: A microelectromechanical system (MEMS) device includes a substrate and a movable element at least partially suspended above the substrate and having at least one degree of freedom. The MEMS device further includes a protrusion extending from the substrate and configured to contact the movable element when the movable element moves in the at least one degree of freedom, wherein the protrusion comprises a surface having a water contact angle of higher than about 15° measured in air.
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公开(公告)号：US09791406B2
公开(公告)日：2017-10-17
申请号：US15284283
申请日：2016-10-03
Inventor： Alexander Kalnitsky , Yi-Shao Liu , Kai-Chih Liang , Chia-Hua Chu , Chun-Ren Cheng , Chun-Wen Cheng
IPC: H01L51/05 , G01N27/414 , H01L21/84 , H01L27/12 , H01L51/00
CPC classification number: G01N27/4145 , G01N27/414 , G01N27/4148 , H01L21/84 , H01L27/1203 , H01L51/0093
Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.
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公开(公告)号：US20170260042A1
公开(公告)日：2017-09-14
申请号：US15066799
申请日：2016-03-10
Inventor： Yu-Chia Liu , Chia-Hua Chu , Chun-Wen Cheng
CPC classification number: B81B7/0006 , B81B7/0051 , B81B2201/0257 , B81B2201/0264 , B81B2201/0271 , B81C1/00246 , B81C2201/0132 , B81C2201/0133 , B81C2201/0176 , B81C2201/0181 , B81C2201/112 , B81C2203/0714 , B81C2203/0735
Abstract: Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.
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公开(公告)号：US09691725B2
公开(公告)日：2017-06-27
申请号：US15076003
申请日：2016-03-21
Inventor： Kuei-Sung Chang , Chun-wen Cheng , Alexander Kalnitsky , Chia-Hua Chu
IPC: H01L23/48 , H01L23/00 , H01L25/065 , H01L23/64 , H01L25/16 , H01L25/00 , H01L21/768
CPC classification number: H01L24/09 , H01L21/76898 , H01L23/481 , H01L23/64 , H01L24/08 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/80 , H01L24/81 , H01L24/82 , H01L24/83 , H01L24/92 , H01L25/0657 , H01L25/16 , H01L25/50 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/08145 , H01L2224/13022 , H01L2224/13124 , H01L2224/13147 , H01L2224/24011 , H01L2224/24051 , H01L2224/24105 , H01L2224/24145 , H01L2224/80896 , H01L2224/81 , H01L2224/821 , H01L2224/9202 , H01L2224/9212 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2225/06565 , H01L2924/00014 , H01L2924/01322 , H01L2924/1205 , H01L2924/1305 , H01L2924/13091 , H01L2924/15787 , H01L2924/00 , H01L2224/82 , H05K3/4661 , H01L2224/05552 , H01L2224/8203 , H01L2224/80001
Abstract: The present disclosure provides one embodiment of a stacked semiconductor device. The stacked semiconductor device includes a first substrate; a first bond pad over the first substrate; a second substrate including a second electrical device fabricated thereon; a second bond pad over the second electrical device over the second substrate, the second bond pad electrically connecting to the second electrical device; a second insulation layer over the second bond pad having a top surface, the second insulation layer being bonded toward the first bond pad of the first substrate; and a through-substrate-via (“TSV”) extending from a surface opposite to the first bond pad through the first substrate and through the top surface of the second insulation layer to the second bond pad.
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公开(公告)号：US09550666B2
公开(公告)日：2017-01-24
申请号：US14613740
申请日：2015-02-04
Inventor： Chung-Hsien Lin , Chia-Hua Chu , Chun-Wen Cheng
CPC classification number: B81B7/0058 , B81C1/00333 , B81C1/0038 , B81C2203/0136 , B81C2203/0145 , H01L2924/0002 , H01L2924/00
Abstract: The present disclosure provides a micro-electro-mechanical systems (MEMS) device. In an embodiment, a device includes a substrate; a MEMS structure disposed above a sacrificial layer opening above the substrate; a release aperture disposed at substantially a same level above the sacrificial layer opening as the MEMS structure; a first cap over the MEMS structure and the sacrificial layer opening, a leg of the first cap disposed between the MEMS structure and the release aperture; and a second cap plugging the release aperture.
Abstract translation: 本公开提供了一种微机电系统（MEMS）装置。 在一个实施例中，装置包括基板; 设置在所述衬底上方的牺牲层开口上方的MEMS结构; 释放孔，设置在与所述MEMS结构相似的牺牲层开口上方的基本相同的水平处; MEMS结构和牺牲层开口上的第一盖，设置在MEMS结构和释放孔之间的第一盖的腿; 以及封闭释放孔的第二帽。
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Patent Agency Ranking
公开(公告)号：US09452924B2
公开(公告)日：2016-09-27
申请号：US13650867
申请日：2012-10-12
Inventor： Chia-Hua Chu , Chun-Wen Cheng , Te-Hao Lee , Chung-Hsien Lin
CPC classification number: B81B3/0054 , B81B2201/0235 , B81B2203/0307 , B81B2203/04 , B81B2207/07 , B81C1/00238
Abstract: A method for fabricating a MEMS device includes providing a micro-electro-mechanical system (MEMS) substrate having a sacrificial layer on a first side, providing a carrier including a plurality of cavities, bonding the first side of the MEMS substrate on the carrier, forming a first bonding material layer on a second side of the MEMS substrate, applying a sacrificial layer removal process to the MEMS substrate, providing a semiconductor substrate including a second bonding material layer and bonding the semiconductor substrate on the second side of the MEMS substrate.
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公开(公告)号：US09388040B2
公开(公告)日：2016-07-12
申请号：US14798213
申请日：2015-07-13
Inventor： Chia-Hua Chu , Chun-Wen Cheng
CPC classification number: B81B7/0041 , B81C1/00158 , B81C1/00238 , B81C1/00301 , B81C2201/019 , B81C2203/00 , B81C2203/0714 , B81C2203/0792 , H01L23/10 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/83 , H01L25/50 , H01L2224/04026 , H01L2224/2745 , H01L2224/27452 , H01L2224/27831 , H01L2224/29011 , H01L2224/291 , H01L2224/29124 , H01L2224/29147 , H01L2224/32145 , H01L2224/83805 , H01L2224/8382 , H01L2924/01322 , H01L2924/1461 , H01L2924/00014 , H01L2924/00
Abstract: A stacked semiconductor device includes a CMOS device and a MEMS device. The CMOS device includes a multilayer interconnect with metal elements disposed over the multilayer interconnect. The MEMS device includes metal sections with a first dielectric layer disposed over the metal sections. A cavity in the first dielectric layer exposes portions of the metal sections. A dielectric stop layer is disposed at least over the interior surface of the cavity. A movable structure is disposed over a front surface of the first dielectric layer and suspending over the cavity. The movable structure includes a second dielectric layer over the front surface of the first dielectric layer and suspending over the cavity, metal features over the second dielectric layer, and a flexible dielectric membrane over the metal features. The CMOS device is bonded to the MEMS device with the metal elements toward the flexible dielectric membrane.
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78.发明授权MEMS integrated pressure sensor devices having isotropic cavities and methods of forming same 有权具有各向同性空腔的MEMS集成压力传感器装置及其形成方法公开(公告)号：US09260295B2
公开(公告)日：2016-02-16
申请号：US14331495
申请日：2014-07-15
Inventor： Chia-Hua Chu , Chun-Wen Cheng
CPC classification number: B81B7/02 , B81B2201/0235 , B81B2201/0242 , B81B2201/025 , B81B2201/0264 , B81B2203/0127 , B81B2203/0315 , B81C1/00182 , B81C1/00238 , B81C2201/013 , B81C2201/019 , B81C2203/0118 , B81C2203/0792 , H01L23/10 , H01L24/29 , H01L24/32 , H01L24/83 , H01L25/50 , H01L2224/29011 , H01L2224/29013 , H01L2224/291 , H01L2224/29124 , H01L2224/29144 , H01L2224/32145 , H01L2224/83193 , H01L2224/83805 , H01L2924/01322 , H01L2924/1461 , H01L2224/3012 , H01L2924/00012 , H01L2924/01029 , H01L2924/00
Abstract: A method embodiment includes providing a MEMS wafer comprising an oxide layer, a MEMS substrate, a polysilicon layer. A carrier wafer comprising a first cavity formed using isotropic etching is bonded to the MEMS, wherein the first cavity is aligned with an exposed first portion of the polysilicon layer. The MEMS substrate is patterned, and portions of the sacrificial oxide layer are removed to form a first and second MEMS structure. A cap wafer including a second cavity is bonded to the MEMS wafer, wherein the bonding creates a first sealed cavity including the second cavity aligned to the first MEMS structure, and wherein the second MEMS structure is disposed between a second portion of the polysilicon layer and the cap wafer. Portions of the carrier wafer are removed so that first cavity acts as a channel to ambient pressure for the first MEMS structure.
Abstract translation: 方法实施例包括提供包括氧化物层，MEMS衬底，多晶硅层的MEMS晶片。 包括使用各向同性蚀刻形成的第一空腔的载体晶片被结合到MEMS，其中第一空腔与多晶硅层的暴露的第一部分对准。 图案化MEMS衬底，并且去除牺牲氧化物层的部分以形成第一和第二MEMS结构。 包括第二腔的盖晶片被结合到MEMS晶片，其中所述接合产生包括与所述第一MEMS结构对准的所述第二腔的第一密封腔，并且其中所述第二MEMS结构设置在所述多晶硅层的第二部分和 盖晶圆。 去除载体晶片的部分，使得第一腔作为第一MEMS结构的环境压力的通道。
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公开(公告)号：US20150329351A1
公开(公告)日：2015-11-19
申请号：US14137672
申请日：2013-12-20
Inventor： Chun-Wen Cheng , Yi-Chuan Teng , Hung-Chia Tsai , Chia-Hua Chu
CPC classification number: B81C1/0023 , B81B7/007 , B81B2201/0235 , B81B2201/0242 , B81B2207/096 , B81C1/00238 , B81C1/00301 , H01L21/76898 , H01L2224/11 , H01L2924/16235
Abstract: A vacuum sealed MEMS and CMOS package and a process for making the same may include a capping wafer having a surface with a plurality of first cavities, a first device having a first surface with a second plurality of second cavities, a hermetic seal between the first surface of the first device and the surface of the capping wafer, and a second device having a first surface bonded to a second surface of the first device. The second device is a CMOS device with conductive through vias connecting the first device to a second surface of the second device, and conductive bumps on the second surface of the second device. Conductive bumps connect to the conductive through vias and wherein a plurality of conductive bumps connect to the second device. The hermetic seal forms a plurality of micro chambers between the capping wafer and the first device.
Abstract translation: 真空密封的MEMS和CMOS封装及其制造方法可以包括具有多个第一腔的表面的封盖晶片，具有第二表面和第二多个第二腔的第一器件，第一和第二腔之间的密封 第一装置的表面和封盖晶片的表面，以及具有结合到第一装置的第二表面的第一表面的第二装置。 第二装置是CMOS器件，其具有将第一器件连接到第二器件的第二表面的导电通孔，以及在第二器件的第二表面上的导电凸块。 导电凸块连接到导电通孔，并且其中多个导电凸块连接到第二装置。 密封密封件在封盖晶片和第一装置之间形成多个微室。
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80.发明申请Dual Layer Microelectromechanical Systems Device and Method of Manufacturing Same 有权双层微机电系统设备及其制造方法相同公开(公告)号：US20150217996A1
公开(公告)日：2015-08-06
申请号：US14685309
申请日：2015-04-13
Inventor： Chia-Hua Chu , Chun-Wen Cheng , Jiou-Kang Lee , Kai-Chih Liang , Chung-Hsien Lin , Te-Hao Lee
IPC: B81C1/00
CPC classification number: B81C1/00269 , B81B2201/0235 , B81B2201/0242 , B81B2201/0257 , B81B2203/0307 , B81B2207/012 , B81C1/00039 , B81C1/00261 , B81C2203/035
Abstract: Exemplary microelectromechanical system (MEMS) devices, and methods for fabricating such are disclosed. An exemplary method includes providing a silicon-on-insulator (SOI) substrate, wherein the SOI substrate includes a first silicon layer separated from a second silicon layer by an insulator layer; processing the first silicon layer to form a first structure layer of a MEMS device; bonding the first structure layer to a substrate; and processing the second silicon layer to form a second structure layer of the MEMS device.
Abstract translation: 公开了示例性微机电系统（MEMS）装置及其制造方法。 一种示例性方法包括提供绝缘体上硅（SOI）衬底，其中SOI衬底包括通过绝缘体层与第二硅层分离的第一硅层; 处理所述第一硅层以形成MEMS器件的第一结构层; 将第一结构层接合到基板上; 以及处理所述第二硅层以形成所述MEMS器件的第二结构层。
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