公开(公告)号：US20080296616A1

公开(公告)日：2008-12-04

申请号：US11809958

申请日：2007-06-04

申请人： Tingkai Li ,  Douglas J. Tweet ,  Jer-Shen Maa ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Douglas J. Tweet ,  Jer-Shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L21/20 ,  H01L29/20

CPC分类号： H01L21/02381 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/0251 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/02647

摘要： A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate that is heated to a temperature in a range of about 300 to 800° C., and a first film is formed in compression overlying the Si substrate. The first film material may be InP, SiGe, GaP, GaAs, AlN, AlGaN, an AlN/graded AlGaN (Al1−xGaxN (0

摘要翻译： 提供了一种在硅（Si）和氮化镓（GaN）膜之间形成匹配的热膨胀界面的方法。 该方法提供加热至约300至800℃范围内的温度的（111）Si衬底，并且第一膜以压缩形式覆盖Si衬底。 第一膜材料可以是InP，SiGe，GaP，GaAs，AlN，AlGaN，AlN /分级AlGaN（Al1-xGaxN（0

公开(公告)号：US07402456B2

公开(公告)日：2008-07-22

申请号：US10831677

申请日：2004-04-23

申请人： Wei-Wei Zhuang ,  Tingkai Li ,  Sheng Teng Hsu ,  Fengyan Zhang

发明人： Wei-Wei Zhuang ,  Tingkai Li ,  Sheng Teng Hsu ,  Fengyan Zhang

IPC分类号： H01L21/44

CPC分类号： H01L45/04 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/31 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1608

摘要： A method is provided for forming a Pr0.3Ca0.7MnO3 (PCMO) thin film with crystalline structure-related memory resistance properties. The method comprises: forming a PCMO thin film with a first crystalline structure; and, changing the resistance state of the PCMO film using pulse polarities responsive to the first crystalline structure. In one aspect the first crystalline structure is either amorphous or a weak-crystalline. Then, the resistance state of the PCMO film is changed in response to unipolar pulses. In another aspect, the PCMO thin film has either a polycrystalline structure. Then, the resistance state of the PCMO film changes in response to bipolar pulses.

摘要翻译： 提供了一种用于形成具有结晶结构相关的记忆电阻性质的Pr 0.3M 3 Ca 0.7 MnO 3（PCMO）薄膜的方法。 该方法包括：形成具有第一晶体结构的PCMO薄膜; 并且使用响应于第一晶体结构的脉冲极性来改变PCMO膜的电阻状态。 在一个方面，第一晶体结构是无定形或弱结晶。 然后，响应于单极脉冲改变PCMO膜的电阻状态。 另一方面，PCMO薄膜具有多晶结构。 然后，PCMO膜的电阻状态响应于双极性脉冲而改变。

公开(公告)号：US20080164577A1

公开(公告)日：2008-07-10

申请号：US11649634

申请日：2007-01-04

申请人： Tingkai Li ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L21/3065 ,  H01L29/06

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L21/306 ,  H01L29/0669 ,  H01L29/0673 ,  Y10S977/743

摘要： An array of submicron silicon (Si) tubes is provided with a method for patterning submicron Si tubes. The method provides a Si substrate, and forms a silicon dioxide film overlying the Si substrate. An array of silicon dioxide rods is formed from the silicon dioxide film, and Si3N4 tubes are formed surrounding the silicon dioxide rods. The silicon dioxide rods are etched away. Then, exposed regions of the Si substrate are etched, forming Si tubes underlying the Si3N4 tubes. Finally, the Si3N4 tubes are removed.

摘要翻译： 亚微米硅（Si）管的阵列具有用于构图亚微米Si管的方法。 该方法提供Si衬底，并形成覆盖Si衬底的二氧化硅膜。 由二氧化硅膜形成二氧化硅棒的阵列，并且在二氧化硅棒周围形成Si 3 N 4 N 4管。 二氧化硅棒被蚀刻掉。 然后，蚀刻Si衬底的暴露区域，形成Si 3 N 4 N 4管子下面的Si管。 最后，去除Si 3 N 4 N 4管。

公开(公告)号：US07259055B2

公开(公告)日：2007-08-21

申请号：US11066713

申请日：2005-02-24

申请人： Tingkai Li ,  Pooran Chandra Joshi ,  Wei Gao ,  Yoshi Ono ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Pooran Chandra Joshi ,  Wei Gao ,  Yoshi Ono ,  Sheng Teng Hsu

IPC分类号： H01L21/8238

CPC分类号： H01L31/03046 ,  Y02E10/544 ,  Y02P70/521

摘要： A method for forming a high-luminescence Si electroluminescence (EL) phosphor is provided, with an EL device made from the Si phosphor. The method comprises: depositing a silicon-rich oxide (SRO) film, with Si nanocrystals, having a refractive index in the range of 1.5 to 2.1, and a porosity in the range of 5 to 20%; and, post-annealing the SRO film in an oxygen atmosphere. DC-sputtering or PECVD processes can be used to deposit the SRO film. In one aspect the method further comprises: HF buffered oxide etching (BOE) the SRO film; and, re-oxidizing the SRO film, to form a SiO2 layer around the Si nanocrystals in the SRO film. In one aspect, the SRO film is re-oxidized by annealing in an oxygen atmosphere. In this manner, a layer of SiO2 is formed around the Si nanocrystals having a thickness in the range of 1 to 5 nanometers (nm).

摘要翻译： 提供一种用于形成高发光Si电致发光（EL）荧光体的方法，其具有由Si荧光体制成的EL器件。 该方法包括：用Si纳米晶体沉积富含氧的氧化物（SRO）膜，折射率在1.5至2.1范围内，孔隙率在5至20％的范围内; 并且在氧气氛中对SRO膜进行后退火。 DC溅射或PECVD工艺可用于沉积SRO膜。 在一个方面，该方法还包括：HF缓冲氧化物蚀刻（BOE）SRO膜; 并且再次氧化SRO膜，以在SRO膜中的Si纳米晶体周围形成SiO 2层。 在一个方面，SRO膜通过在氧气气氛中退火再次氧化。 以这种方式，在具有1至5纳米（nm）范围内的厚度的Si纳米晶体周围形成SiO 2层。

公开(公告)号：US07008801B2

公开(公告)日：2006-03-07

申请号：US10453831

申请日：2003-06-02

申请人： Tingkai Li ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Sheng Teng Hsu

IPC分类号： H01L21/00

CPC分类号： H01L21/28273 ,  C23C16/0272 ,  C23C16/40 ,  C23C16/56 ,  H01L21/28194 ,  H01L21/28291 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517

摘要： A method of forming a ferroelectric thin film on a high-k layer includes preparing a silicon substrate; forming a high-k layer on the substrate; depositing a seed layer of ferroelectric material at a relatively high temperature on the high-k layer; depositing a top layer of ferroelectric material on the seed layer at a relatively low temperature; and annealing the substrate, the high-k layer and the ferroelectric layers to form a ferroelectric thin film.

公开(公告)号：US06939724B2

公开(公告)日：2005-09-06

申请号：US10640770

申请日：2003-08-13

申请人： Wei-Wei Zhuang ,  Tingkai Li ,  David R. Evans ,  Sheng Teng Hsu ,  Wei Pan

发明人： Wei-Wei Zhuang ,  Tingkai Li ,  David R. Evans ,  Sheng Teng Hsu ,  Wei Pan

IPC分类号： H01L27/04 ,  H01L21/20 ,  H01L21/822 ,  H01L45/00 ,  H01L21/00

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1608

摘要： A method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer includes depositing, by MOCVD, a seed layer of PCMO, in highly crystalline form, thin film, having a thickness of between about 50 Å to 300 Å, depositing a second PCMO thin film layer on the seed layer, by spin coating, having a thickness of between about 500 Å to 3000 Å, to form a combined PCMO layer; increasing the resistance of the combined PCMO film in a semiconductor device by applying a negative electric pulse of between about −4V to −5V, having a pulse width of between about 75 nsec to 1 μsec; and decreasing the resistance of the combined PCMO layer in a semiconductor device by applying a positive electric pulse of between about +2.5V to +4V, having a pulse width greater than 2.0 μsec.

公开(公告)号：US06927074B2

公开(公告)日：2005-08-09

申请号：US10442627

申请日：2003-05-21

申请人： Sheng Teng Hsu ,  Tingkai Li ,  David R. Evans

发明人： Sheng Teng Hsu ,  Tingkai Li ,  David R. Evans

IPC分类号： H01L27/10 ,  G11C11/15 ,  G11C13/00 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  H01L21/00

CPC分类号： G11C13/0007 ,  B82Y10/00 ,  G11C11/15 ,  G11C2213/31 ,  G11C2213/52 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/147

摘要： An asymmetric memory cell and method for forming an asymmetric memory cell are provided. The method comprises: forming a bottom electrode having a first area; forming an electrical pulse various resistance (EPVR) material overlying the bottom electrode; forming a top electrode overlying the EPVR layer having a second area, less than the first area. In some aspects the second area is at least 20% smaller than the first area. The EPVR is a material such as colossal magnetoresistance (CMR), high temperature super conducting (HTSC), or perovskite metal oxide materials. The method further comprises: inducing an electric field between the electrodes; inducing current flow through the EPVR adjacent the top electrode; and, in response to inducing current flow through the EPVR adjacent the top electrode, modifying the resistance of the EPVR. Typically, the resistance is modified within the range of 100 ohms to 10 mega-ohms.

摘要翻译： 提供了一种用于形成非对称存储单元的非对称存储单元和方法。 该方法包括：形成具有第一区域的底部电极; 形成覆盖底部电极的各种电阻（EPVR）材料的电脉冲; 形成覆盖在EPVR层上的顶部电极，其具有小于第一区域的第二区域。 在一些方面，第二区域比第一区域小至少20％。 EPVR是诸如巨磁阻（CMR），高温超导（HTSC）或钙钛矿金属氧化物材料的材料。 该方法还包括：在电极之间引入电场; 通过邻近顶部电极的EPVR引起电流流动; 并且响应于通过与顶部电极相邻的EPVR的电流流动，修改EPVR的电阻。 通常，电阻在100欧姆到10兆欧姆的范围内被修改。

公开(公告)号：US06762063B2

公开(公告)日：2004-07-13

申请号：US10395368

申请日：2003-03-24

申请人： Sheng Teng Hsu ,  Fengyan Zhang ,  Tingkai Li

发明人： Sheng Teng Hsu ,  Fengyan Zhang ,  Tingkai Li

IPC分类号： H01L2100

CPC分类号： H01L29/6684 ,  H01L21/28291 ,  H01L29/78391

摘要： A method of fabricating a non-volatile ferroelectric memory transistor includes forming a bottom electrode; depositing a ferroelectric layer over an active region beyond the margins of the bottom electrode; depositing a top electrode on the ferroelectric layer; and metallizing the structure to form a source electrode, a gate electrode and a drain electrode. A non-volatile ferroelectric memory transistor includes a bottom electrode formed above a gate region, wherein the bottom electrode has a predetermined area within a peripheral boundary; a ferroelectric layer extending over and beyond the bottom electrode peripheral boundary; and a top electrode formed on said ferroelectric layer.

摘要翻译： 制造非挥发性铁电存储晶体管的方法包括：形成底电极; 在超过底部电极的边缘的有源区域上沉积铁电层; 在铁电层上沉积顶部电极; 并且将该结构金属化以形成源电极，栅电极和漏电极。 非挥发性铁电存储晶体管包括形成在栅极区域上方的底部电极，其中底部电极在外围边界内具有预定区域; 延伸超过底部电极周边边界的铁电层; 以及形成在所述铁电层上的顶部电极。

公开(公告)号：US06673664B2

公开(公告)日：2004-01-06

申请号：US09978487

申请日：2001-10-16

申请人： Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang

发明人： Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang

IPC分类号： H01L218238

CPC分类号： H01L29/51 ,  H01L21/28291 ,  H01L21/31691 ,  H01L27/11502 ,  H01L27/11507 ,  H01L29/516

摘要： A method of making a self-aligned ferroelectric memory transistor includes preparing a substrate, shallow trench isolation, n the polysilicon; and forming a gate stack, including: depositing a layer of silicon nitride; selectively etching the silicon nitride, the bottom electrode and the polysilicon; selectively etching the polysilicon to the level of the first dielectric layer; and implanting and activating ions to form a source region and a drain region; forming a sidewall barrier layer; depositing a layer of ferroelectric material; forming a top electrode structure on the ferroelectric material; and finishing the structure, including passivation, oxide depositing and metallization.

摘要翻译： 制造自对准铁电存储晶体管的方法包括制备衬底，浅沟槽隔离，n多晶硅; 以及形成栅叠层，包括：沉积氮化硅层; 选择性地蚀刻氮化硅，底部电极和多晶硅; 选择性地将多晶硅蚀刻到第一介电层的水平面; 以及植入和激活离子以形成源区和漏区; 形成侧壁阻挡层; 沉积一层铁电材料; 在铁电材料上形成顶部电极结构; 并完成结构，包括钝化，氧化物沉积和金属化。

公开(公告)号：US06616857B2

公开(公告)日：2003-09-09

申请号：US09942203

申请日：2001-08-29

申请人： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

IPC分类号： H01B108

CPC分类号： H01L21/31691 ,  C23C16/40 ,  H01L21/31604 ,  Y10S438/933 ,  Y10T428/12674 ,  Y10T428/12701 ,  Y10T428/12875

摘要： A ferroelectric Pb5Ge3O11 (PGO) thin film is provided with a metal organic vapor deposition (MOCVD) process and RTP (Rapid Thermal Process) annealing techniques. The PGO film is substantially crystallization with c-axis orientation at temperature between 450 and 650° C. The PGO film has an average grain size of about 0.5 microns, with a deviation in grain size uniformity of less than 10%. Good ferroelectric properties are obtained for a 150 nm thick film with Ir electrodes. The films also show fatigue-free characteristics: no fatigue was observed up to 1×109 switching cycles. The leakage currents increase with increasing applied voltage, and are about 3.6×10−7 A/cm2 at 100 kV/cm. The dielectric constant shows a behavior similar to most ferroelectric materials, with a maximum dielectric constant of about 45. These high quality MOCVD Pb5Ge3O11 films can be used for high density single transistor ferroelectric memory applications because of the homogeneity of the PGO film grain size.

摘要翻译： 铁电Pb5Ge3O11（PGO）薄膜提供金属有机气相沉积（MOCVD）工艺和RTP（快速热处理）退火技术。 PGO膜在450-650℃的温度下基本上以c轴取向结晶.PGO膜的平均粒径为约0.5微米，晶粒尺寸均匀度的偏差小于10％。 对于具有Ir电极的150nm厚的膜，获得良好的铁电性能。 这些胶片还显示出无疲劳特性：在1x109个开关周期内没有观察到疲劳。 泄漏电流随着施加电压的增加而增加，在100kV / cm时为约3.6×10 -7 A / cm 2。 介电常数表现出类似于大多数铁电材料的行为，其最大介电常数为约45.这些高质量的MOCVD Pb5Ge3O11膜可用于高密度单晶硅铁氧体存储器应用，因为PGO膜晶粒尺寸的均匀性。