公开(公告)号：US20080142983A1

公开(公告)日：2008-06-19

申请号：US12036887

申请日：2008-02-25

Applicant: Tongbi Jiang ,  Li Li

Inventor： Tongbi Jiang ,  Li Li

IPC: H01L23/48 ,  H01L21/44 ,  B05C11/00

CPC classification number: H01L24/05 ,  H01L21/02052 ,  H01L21/288 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/7685 ,  H01L24/03 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01016 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  Y10S134/902

Abstract: A method and apparatus is disclosed for sequential processing of integrated circuits, particularly for conductively passivating a contact pad with a material which resists formation of resistive oxides. In particular, a tank is divided into three compartments, each holding a different solution: a lower compartment and two upper compartments divided by a barrier, which extends across and partway down the tank. The solutions have different densities and therefore separate into different layers. In the illustrated embodiment, integrated circuits with patterned contact pads are passed through one of the upper compartments, in which oxide is removed from the contact pads. Continuing downward into the lower compartment and laterally beneath the barrier, a protective layer is selectively formed on the insulating layer surrounding the contact pads. As the integrated circuits are moved upwardly into the second upper compartment, a conducting monomer selectively forms on the contact pads prior to any exposure to air. The integrated circuits can then be transferred to an ozone chamber where polymerization results in a conductive passivation layer on the contact pad.

Abstract translation: 公开了用于集成电路的顺序处理的方法和装置，特别是用抵抗形成电阻氧化物的材料导电地钝化接触焊盘。 特别地，罐被分成三个隔室，每个隔间都有一个不同的解决方案：一个下隔室和两个隔离隔间的隔离隔板，两个隔间延伸横跨槽和一半的槽。 溶液具有不同的密度，因此分离成不同的层。 在所示实施例中，具有图案化接触焊盘的集成电路通过上隔室之一，其中氧化物从接触焊盘移除。 继续向下进入下隔室并在屏障下方横向放置，在围绕接触垫的绝缘层上选择性地形成保护层。 当集成电路向上移动到第二上隔室中时，在任何暴露于空气之前，在接触焊盘上选择性地形成导电单体。 然后可以将集成电路转移到臭氧室，其中聚合导致接触焊盘上的导电钝化层。

公开(公告)号：US20080054432A1

公开(公告)日：2008-03-06

申请号：US11514819

申请日：2006-09-01

Applicant: David J. Corisis ,  Tongbi Jiang ,  Shijian Luo

Inventor： David J. Corisis ,  Tongbi Jiang ,  Shijian Luo

IPC: H01L23/02

CPC classification number: H01L23/49575 ,  H01L23/49506 ,  H01L23/49531 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stacked semiconductor die assembly includes at least two partially offset semiconductor dice with bond pads located adjacent at least one peripheral side thereof supported on a redistribution element formed of a material of substantially similar CTE to that of the dice, and a paddle-less lead frame secured to the redistribution element during fabrication, including encapsulation. The assembly is configured to be substantially vertically symmetrical with respect to inner ends of lead fingers of the lead frame to facilitate uniform encapsulant flow. The semiconductor die assembly may be configured in a package with leads extending from two sides thereof, such as a thin small outline package (TSOP), or four sides thereof, such as a quad flat pack (QFP).

Abstract translation: 堆叠的半导体管芯组件包括至少两个部分偏移的半导体管芯，其具有位于邻近其至少一个外围侧的接合焊盘，所述接合焊盘支撑在由与所述管芯相当的CTE的材料形成的再分配元件上，以及无桨引线框架 在制造期间固定到再分配元件，包括封装。 组件被构造成相对于引线框架的引线指的内端基本上垂直对称，以促进均匀的密封剂流动。 半导体管芯组件可以被构造成具有从其两侧延伸的引线的封装，诸如薄的小外形封装（TSOP）或其四边，例如四边形封装（QFP）。

公开(公告)号：US07297412B2

公开(公告)日：2007-11-20

申请号：US11386208

申请日：2006-03-22

Applicant: Michael E. Connell ,  Tongbi Jiang

Inventor： Michael E. Connell ,  Tongbi Jiang

IPC: B32B15/08 ,  B21D39/00

CPC classification number: H01L21/6836 ,  H01L21/6835 ,  H01L21/78 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68322 ,  H01L2221/68327 ,  H01L2224/274 ,  H01L2224/29007 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/07802 ,  H01L2924/14 ,  Y10S438/976 ,  Y10T156/1082 ,  Y10T156/1092 ,  Y10T428/12535 ,  Y10T428/1443 ,  Y10T428/1457 ,  Y10T428/1471 ,  Y10T428/1495 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Manufacture of stacked microelectronic devices is facilitated by producing subassemblies wherein adhesive pads are applied to the back surfaces of a plurality of microelectronic components in a batch fashion. In one embodiment, an adhesive payer is applied on a rear surface of a wafer. A plurality of spaced-apart adhesive pads are defined within the adhesive layer. Each adhesive pad may cover less than the entire back surface area of the component to which it is attached. A mounting member (e.g., dicing tape) may be attached to the adhesive layer and, in some embodiments, the adhesive layer may be treated so that the mounting member is less adherent to the adhesive pads than to other parts of the adhesive layer, easing removal of the adhesive pads with the microelectronic components.

Abstract translation: 堆叠的微电子器件的制造通过生产其中粘合垫以批次方式施加到多个微电子部件的背面的子组件而得到促进。 在一个实施例中，粘合剂支付者被施加在晶片的后表面上。 多个间隔开的粘合剂垫限定在粘合剂层内。 每个粘合垫可以覆盖小于其所附接的部件的整个后表面区域。 安装构件（例如，切割带）可以附接到粘合剂层，并且在一些实施例中，可以对粘合剂层进行处理，使得安装构件比粘合剂层的其它部分更不粘附到粘合剂垫，减轻 用微电子部件去除粘合垫。

公开(公告)号：US07253089B2

公开(公告)日：2007-08-07

申请号：US10867023

申请日：2004-06-14

Applicant: Shijian Luo ,  Tongbi Jiang

Inventor： Shijian Luo ,  Tongbi Jiang

IPC: H01L21/44

CPC classification number: H01L24/10 ,  H01L21/561 ,  H01L21/563 ,  H01L24/13 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Microfeature devices, microfeature workpieces, and methods for manufacturing microfeature devices and microfeature workpieces are disclosed herein. The microfeature workpieces have an integrated circuit, a surface, and a plurality of interconnect elements projecting from the surface and arranged in arrays on the surface. In one embodiment, a method includes forming a coating on the interconnect elements of the microfeature workpiece, producing a layer over the surface of the microfeature workpiece after forming the coating, and removing the coating from at least a portion of the individual interconnect elements. The coating has a surface tension less than a surface tension of the interconnect elements to reduce the extent to which the material in the layer wicks up the interconnect elements and produces a fillet at the base of the individual interconnect elements.

公开(公告)号：US07213331B2

公开(公告)日：2007-05-08

申请号：US10689471

申请日：2003-10-20

Applicant: Tongbi Jiang ,  Edward A. Schrock

Inventor： Tongbi Jiang ,  Edward A. Schrock

IPC: H05K3/34

CPC classification number: H01L24/83 ,  H01L24/31 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/095 ,  H05K3/1216 ,  H05K3/4007 ,  H05K2201/035 ,  H05K2201/0367 ,  H05K2201/09745 ,  H05K2203/167 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49181 ,  Y10T29/49204 ,  H01L2924/00

Abstract: A method of forming a stencil for the manufacture of semiconductor devices includes defining a plurality of slightly spaced segmental annular openings in a stencil plate. The spacing between the segmental annular openings define spokes extending from a central portion of said stencil connected via those spokes to the rest of the stencil plate. The spokes extend past two adjacent annular segments.

Abstract translation: 形成用于制造半导体器件的模板的方法包括在模板中限定多个稍微间隔开的节段环形开口。 节段环形开口之间的间隔限定了从通过这些轮辐连接到模板的其余部分的所述模板的中心部分延伸的辐条。 轮辐延伸过两个相邻的环形段。

公开(公告)号：US07199463B2

公开(公告)日：2007-04-03

申请号：US11146889

申请日：2005-06-06

Applicant: Tongbi Jiang

Inventor： Tongbi Jiang

IPC: H01L23/12 ,  H01L23/053

CPC classification number: H01L24/16 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2224/16237 ,  H01L2224/29013 ,  H01L2224/29036 ,  H01L2224/2919 ,  H01L2224/30131 ,  H01L2224/32014 ,  H01L2224/48 ,  H01L2224/73203 ,  H01L2224/81136 ,  H01L2224/81192 ,  H01L2224/81903 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01045 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/45099

Abstract: A semiconductor package structure for a ball grid array type package using a plurality of pieces of adhesive elastomer film to attach a semiconductor die to a substrate having conductive traces in order to alleviate thermal mismatch stress between the semiconductor die and the printed circuit board to which the packaged device is soldered, while maintaining the reliability of the packaged device itself.

Abstract translation: 一种用于球栅阵列型封装的半导体封装结构，其使用多个粘合弹性体膜将半导体管芯附着到具有导电迹线的衬底，以便减轻半导体管芯和印刷电路板之间的热失配应力， 封装的器件被焊接，同时保持封装器件本身的可靠性。

公开(公告)号：US20060189118A1

公开(公告)日：2006-08-24

申请号：US11407435

申请日：2006-04-20

Applicant: Shijian Luo ,  Tongbi Jiang

Inventor： Shijian Luo ,  Tongbi Jiang

IPC: H01L21/44

CPC classification number: H01L24/10 ,  H01L21/561 ,  H01L21/563 ,  H01L24/13 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Microfeature devices, microfeature workpieces, and methods for manufacturing microfeature devices and microfeature workpieces are disclosed herein. The microfeature workpieces have an integrated circuit, a surface, and a plurality of interconnect elements projecting from the surface and arranged in arrays on the surface. In one embodiment, a method includes forming a coating on the interconnect elements of the microfeature workpiece, producing a layer over the surface of the microfeature workpiece after forming the coating, and removing the coating from at least a portion of the individual interconnect elements. The coating has a surface tension less than a surface tension of the interconnect elements to reduce the extent to which the material in the layer wicks up the interconnect elements and produces a fillet at the base of the individual interconnect elements.

公开(公告)号：US07095095B2

公开(公告)日：2006-08-22

申请号：US10879372

申请日：2004-06-28

Applicant: Tongbi Jiang ,  Zhiping Yin

Inventor： Tongbi Jiang ,  Zhiping Yin

IPC: H01L23/58

CPC classification number: H01L29/7842 ,  H01L21/3221 ,  H01L23/4951 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: The invention includes a semiconductor construction. The construction has a semiconductor material die with a front surface, a back surface in opposing relation to the front surface, and a thickness of less than 400 microns between the front and back surfaces. The construction also has circuitry associated with the die and over the front surface of the die, and a layer touching the back surface of the die. The layer can correspond to getter-inducing material and/or to a stress-inducing material. The layer can have a composition which includes silicon dioxide and/or silicon nitride. The composition can include one or more hydrogen isotopes, and the hydrogen isotopes can have a higher abundance of deuterium than the natural abundance of deuterium.

Abstract translation: 本发明包括半导体结构。 该结构具有半导体材料模具，其具有前表面，与前表面相对的后表面，并且在前表面和后表面之间的厚度小于400微米。 该结构还具有与管芯相连的电路和管芯前表面上的电路，以及接触管芯背面的层。 该层可以对应于吸气剂诱导材料和/或对应力诱导材料。 该层可以具有包括二氧化硅和/或氮化硅的组成。 该组合物可以包括一种或多种氢同位素，氢同位素可以具有比氘天然丰度更高的氘丰度。

公开(公告)号：US07094628B2

公开(公告)日：2006-08-22

申请号：US10823047

申请日：2004-04-13

Applicant: Tongbi Jiang ,  Curtis Hollingshead ,  Warren M. Farnworth

Inventor： Tongbi Jiang ,  Curtis Hollingshead ,  Warren M. Farnworth

IPC: H01L21/44

CPC classification number: H01L21/563 ,  H01L23/295 ,  H01L24/29 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83191 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2224/27 ,  H01L2224/11 ,  H01L2224/05599

Abstract: Underfill compounds including electrically charged filler elements, microelectronic devices having underfill compounds including electrically charged filler elements, and methods of disposing underfill including electrically charged filler elements on microelectronic devices are disclosed herein. In one embodiment, a microelectronic device includes a microelectronic component, a plurality of electrical couplers carried by the microelectronic component, and an underfill layer covering at least a portion of the electrical couplers. The underfill layer comprises a binder and a plurality of electrically charged filler elements in the binder. The underfill layer can include a first zone having a first concentration of electrically charged filler elements and a second zone having a second concentration of electrically charged filler elements different than the first concentration.

Abstract translation: 本文公开了包括带电填充元件的底部填充化合物，具有底部填充化合物的微电子器件，包括带电荷的填料元件，以及在微电子器件上设置包含充电填充元素的底部填充剂的方法。 在一个实施例中，微电子器件包括微电子部件，由微电子部件承载的多个电耦合器以及覆盖电耦合器的至少一部分的底部填充层。 底部填充层包括粘合剂和粘合剂中的多个带电荷的填料元素。 底部填充层可以包括具有第一浓度的带电填充元件的第一区域和具有不同于第一浓度的带电荷填充元件的第二浓度的第二区域。

公开(公告)号：US07071078B2

公开(公告)日：2006-07-04

申请号：US10933889

申请日：2004-09-02

Applicant: W. Jeff Reeder ,  Tongbi Jiang

Inventor： W. Jeff Reeder ,  Tongbi Jiang

IPC: H01L21/30 ,  H01L21/46

CPC classification number: H01L24/83 ,  H01L21/67132 ,  H01L23/3737 ,  H01L23/4951 ,  H01L23/49513 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/75 ,  H01L25/50 ,  H01L2224/05599 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/8319 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/351 ,  H01R4/04 ,  H05K3/0058 ,  H05K3/305 ,  H05K3/386 ,  H05K2203/0278 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for securing two or more semiconductor device components to one another is provided. A hybrid adhesive material, including a pressure-sensitive component and a curable component, is used to at least temporarily secure the semiconductor device components to each other. The pressure-sensitive component of the hybrid adhesive material temporarily secures the semiconductor device components to one another. When the semiconductor device components are properly aligned, the curable component of the hybrid adhesive material may be cured to more permanently secure the semiconductor device components to one another. For example, when a thermoset material is used as the curable component, it may be cured by heating, such as at a temperature of lower than about 200° C. and as low as about 120° C. or less.

Abstract translation: 提供了一种用于将两个或更多个半导体器件组件彼此固定的方法。 使用包括压敏部件和可固化部件的混合粘合材料至少将半导体器件部件彼此暂时固定。 混合粘合剂材料的压敏部件将半导体器件部件彼此临时固定。 当半导体器件部件被正确地对准时，混合粘合剂材料的可固化部件可以被固化以将半导体器件部件彼此更加永久地固定。 例如，当将热固性材料用作可固化组分时，其可以通过加热固化，例如在低于约200℃的温度和低至约120℃或更低的温度下固化。