公开(公告)号：US20170236822A1

公开(公告)日：2017-08-17

申请号：US15586285

申请日：2017-05-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/10

CPC classification number: H01L27/0921 ,  H01L21/0243 ,  H01L21/02518 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L29/0607 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/66803

Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; a first bump on the first region; a first doped layer on the first fin-shaped structure and the bump; and a gate structure covering the bump.

公开(公告)号：US20170229345A1

公开(公告)日：2017-08-10

申请号：US15016230

申请日：2016-02-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/7681 ,  H01L21/76813 ,  H01L21/76816 ,  H01L2221/1021

Abstract: A substrate having thereon a first dielectric layer, a second dielectric layer, and a hard mask layer is provided. A partial via is formed in the second dielectric layer and the hard mask layer. A first photoresist pattern with a first trench opening above the partial via and a second trench opening is formed on the hard mask layer. The hard mask layer and the second dielectric layer are etched through the first trench opening and the second trench opening, thereby forming a first dual damascene structure comprising a first trench and a first via, and a second trench in the second dielectric layer, respectively. A second photoresist pattern having a self-aligned via opening above the second trench is formed. The second dielectric layer is etched through the self-aligned via opening, thereby forming a second dual damascene structure comprising the second trench and a second via under the second trench.

公开(公告)号：US20170200633A1

公开(公告)日：2017-07-13

申请号：US15469932

申请日：2017-03-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L21/768

CPC classification number: H01L21/7682 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53295

Abstract: A semiconductor device and a method for manufacturing the same are provided. A semiconductor device includes a substrate, a first capping layer formed above the substrate, a first dielectric layer formed on the first capping layer; a second capping layer formed on the first dielectric layer; a second dielectric layer formed on the second capping layer; a plurality of conducting lines separately formed on the substrate; a third capping layer formed on the conducting lines and the second dielectric layer; and several nano-gaps formed between the adjacent conducting lines, and the nano-gaps being formed in the second dielectric layer, or further extending to the second capping layer or to the first capping layer. The nano-gaps partially open one of the second and first dielectric layers, or the nano-gaps expose the first capping layer or the second capping layer.

公开(公告)号：US09679819B1

公开(公告)日：2017-06-13

申请号：US15062217

申请日：2016-03-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L21/82 ,  H01L21/8238 ,  H01L29/06 ,  H01L27/092 ,  H01L21/02

CPC classification number: H01L27/0921 ,  H01L21/0243 ,  H01L21/02518 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L29/0607 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/66803

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a first bump on the first region and a second bump on the second region; forming a first doped layer on the first fin-shaped structure and the first bump; and forming a second doped layer on the second fin-shaped structure and the second bump.

公开(公告)号：US09673049B2

公开(公告)日：2017-06-06

申请号：US14683120

申请日：2015-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/308

CPC classification number: H01L21/0337 ,  H01L21/3086

Abstract: A manufacturing method of a patterned structure of a semiconductor device includes following steps. A plurality of support features are formed on a substrate. A first conformal spacer layer is formed on the support features and a surface of the substrate, a second conformal spacer layer is formed on the first conformal spacer layer, and a covering layer is formed on the second conformal spacer layer. A gap between the support features is filled with the first conformal spacer layer, the second conformal spacer layer, and the covering layer. A first process is performed to remove a part of the covering layer, the second conformal spacer layer, and the first conformal spacer layer. A second process is performed to remove the support features or the first conformal spacer layer between the support feature and the second conformal spacer layer to expose a part of the surface of the substrate.

公开(公告)号：US20170141221A1

公开(公告)日：2017-05-18

申请号：US14981869

申请日：2015-12-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/768 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L29/785 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795

Abstract: A FinFET is provided. The FinFET includes a substrate. A plurality of fin structures are defined on the substrate. A gate structure crosses each fin structure. Two first recesses are disposed on two sides of the gate structure respectively, wherein each first recess further includes a plurality of second recesses disposed therein, and the position of each second recess corresponds to each fin structure. Two epitaxial layers are disposed at two sides of the gate structure respectively and in the first recesses, each epitaxial layer has a bottom surface including a second concave and convex profile, and each epitaxial layer directly contacts a bottom surface of each first recess and a bottom surface of each second recess.

公开(公告)号：US09627036B2

公开(公告)日：2017-04-18

申请号：US14822911

申请日：2015-08-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tan-Ya Yin ,  Ming-Jui Chen ,  Chia-Wei Huang ,  Yu-Cheng Tung ,  Chin-Sheng Yang

IPC: H01L21/28 ,  H01L23/535 ,  H01L27/11 ,  H01L29/66 ,  G11C11/412 ,  H01L27/02

CPC classification number: G11C11/417 ,  G11C11/412 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1104

Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.

公开(公告)号：US20170069540A1

公开(公告)日：2017-03-09

申请号：US15356671

申请日：2016-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/10 ,  H01L27/088 ,  H01L29/08 ,  H01L29/06 ,  H01L21/324

CPC classification number: H01L21/823431 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02667 ,  H01L21/324 ,  H01L21/3247 ,  H01L21/823412 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: The present invention provides a method for forming a semiconductor structure. Firstly, a substrate is provided, the substrate comprises an insulating layer and at least one first nano channel structure disposed thereon, a first region and a second region being defined on the substrate, next, a hard mask is formed within the first region, afterwards, an etching process is performed, to remove parts of the insulating layer within the second region, an epitaxial process is then performed, to form an epitaxial layer on the first nano channel structure, and an anneal process is performed, to transform the first nano channel structure and the epitaxial layer into a first nanowire structure, wherein the diameter of the first nanowire structure within the first region is different from the diameter of the first nanowire structure within the second region.

Abstract translation: 本发明提供一种形成半导体结构的方法。 首先，提供基板，所述基板包括绝缘层和设置在其上的至少一个第一纳米通道结构，在所述基板上限定第一区域和第二区域，接下来，在所述第一区域内形成硬掩模 执行蚀刻处理，以去除第二区域内的绝缘层的部分，然后进行外延工艺，以在第一纳米通道结构上形成外延层，并进行退火工艺以将第一纳米管 沟道结构和外延层形成第一纳米线结构，其中第一区域内的第一纳米线结构的直径不同于第二区域内的第一纳米线结构的直径。

公开(公告)号：US09590114B1

公开(公告)日：2017-03-07

申请号：US14873617

申请日：2015-10-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7869 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/42384 ,  H01L29/66969 ,  H01L2029/42388

Abstract: A semiconductor device is provided, comprising a substrate with a first insulating film formed thereon, and a transistor formed on the first insulating film. The transistor at least comprises an oxide semiconductor layer formed on the first insulating film, a first gate insulation film formed on the oxide semiconductor layer, a gate electrode formed above the first gate insulation film, and spacers formed on the oxide semiconductor layer. The spacers at least cover the sidewalls of the first gate insulation film and the sidewalls of the gate electrode. The gate electrode has a gate width and the first gate insulation film has a first width, wherein the gate width is different from the first width.

Abstract translation: 提供一种半导体器件，包括其上形成有第一绝缘膜的衬底和形成在第一绝缘膜上的晶体管。 晶体管至少包括形成在第一绝缘膜上的氧化物半导体层，形成在氧化物半导体层上的第一栅极绝缘膜，形成在第一栅极绝缘膜上方的栅电极和形成在氧化物半导体层上的间隔物。 间隔件至少覆盖第一栅绝缘膜的侧壁和栅电极的侧壁。 栅电极具有栅极宽度，第一栅极绝缘膜具有第一宽度，其中栅极宽度与第一宽度不同。

公开(公告)号：US20170025512A1

公开(公告)日：2017-01-26

申请号：US15283445

申请日：2016-10-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/42376 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/4232 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66545

Abstract: A semiconductor device having metal gate includes a substrate, a metal gate formed on the substrate, a pair of spacers formed on sidewalls of the metal gate, a contact etch stop layer (CESL) covering the spacers, an insulating cap layer formed on the metal gate, the spacers and the CESL, and an ILD layer surrounding the metal gate, the spacers, the CESL and the insulating cap layer. The metal gate, the spacers and the CESL include a first width, and the insulating cap layer includes a second width. The second width is larger than the first width. And a bottom of the insulating cap layer concurrently contacts the metal gate, the spacers, the CESL, and the ILD layer.

Abstract translation: 具有金属栅极的半导体器件包括衬底，形成在衬底上的金属栅极，形成在金属栅极的侧壁上的一对间隔物，覆盖间隔物的接触蚀刻停止层（CESL），形成在金属栅极上的绝缘盖层 栅极，间隔物和CESL，以及围绕金属栅极，间隔物，CESL和绝缘帽层的ILD层。 金属栅极，间隔物和CESL包括第一宽度，绝缘帽层包括第二宽度。 第二宽度大于第一宽度。 并且绝缘盖层的底部同时与金属栅极，间隔物，CESL和ILD层接触。