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    Microprocessor that fuses if-then instructions
    71.
    发明授权
    Microprocessor that fuses if-then instructions 有权

    公开(公告)号：US09792121B2

    公开(公告)日：2017-10-17

    申请号：US14066520

    申请日：2013-10-29

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： Terry Parks ,  G. Glenn Henry

    IPC: G06F9/30 ,  G06F9/38

    CPC classification number: G06F9/30145 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3836

    Abstract: A microprocessor includes an instruction translation unit that extracts condition information from the IT instruction and fuses the IT instruction with the first IT block instruction. For each instruction of the IT block, the instruction translation unit: determines a respective condition for the IT block instruction using the condition information extracted from the IT instruction and translates the IT block instruction into a microinstruction. The microinstruction includes the respective condition. Execution units conditionally execute the microinstruction based on the respective condition. For each IT block instruction, the instruction translation unit determines a respective state value using the extracted condition information. The state value comprises the lower eight bits of the IT instruction having the lower five bits left-shifted by N-1 bits, where N indicates a position of the IT block instruction in the IT block.

    Uncore microcode ROM
    75.
    发明授权
    Uncore microcode ROM 有权
    Uncore微码ROM

    公开(公告)号：US09483263B2

    公开(公告)日：2016-11-01

    申请号：US14072428

    申请日：2013-11-05

    Applicant: VIA Technologies, Inc.

    Inventor： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  John D. Bunda ,  Brent Bean

    IPC: G06F9/00 ,  G06F9/44 ,  G06F9/26 ,  G06F9/30

    CPC classification number: G06F9/26 ,  G06F9/30145 ,  G06F9/30174

    Abstract: A microprocessor includes a plurality of processing cores each comprises a corresponding memory physically located inside the core and readable by the core but not readable by the other cores (“core memory”). The microprocessor also includes a memory physically located outside all of the cores and readable by all of the cores (“uncore memory”). For each core, the uncore memory and corresponding core memory collectively provide M words of storage for microcode instructions fetchable by the core as follows: the uncore memory provides J of the M words of microcode instruction storage, and the corresponding core memory provides K of the M words of microcode instruction storage. J, K and M are counting numbers, and M=J+K. The memories are non-architecturally-visible and accessed using a fetch address provided by a non-architectural program counter, and the microcode instructions are non-architectural instructions that implement architectural instructions.

    Abstract translation: 微处理器包括多个处理核心，每个处理核心包括物理上位于核心内并由核心读取但不能被其他核心（“核心存储器”）读取的对应存储器。 微处理器还包括物理上位于所有核心外的所有核心（“非存储器”）可读取的存储器。 对于每个核心，非核存储器和对应的核心存储器共同提供M个字节的存储器，用于由核心获取的微代码指令，如下：非存储器提供微代码指令存储器的M个字节的J，并且相应的核心存储器提供K M码的微码指令存储。 J，K和M是计数数，M = J + K。 存储器是非架构可见的，并且使用由非架构程序计数器提供的提取地址来访问，并且微代码指令是实施架构指令的非架构指令。

    Multi-core synchronization mechanism
    76.
    发明授权
    Multi-core synchronization mechanism 有权
    多核同步机制

    公开(公告)号：US09465432B2

    公开(公告)日：2016-10-11

    申请号：US14281434

    申请日：2014-05-19

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： G. Glenn Henry ,  Terry Parks

    IPC: G06F1/04 ,  G06F1/32 ,  G06F9/52 ,  G06F12/08

    CPC classification number: G06F1/3287 ,  G06F1/04 ,  G06F1/32 ,  G06F9/522 ,  G06F12/0891 ,  G06F2212/1028 ,  G06F2212/60

    Abstract: A microprocessor includes a control unit configured to selectively control a respective clock signal to each of a plurality of processing cores. Each of the processing cores is configured to separately write a value to the control unit. For each core of the plurality of processing cores, the control unit is configured to turn off the respective clock signal to the core in response to the core writing a value to the control unit. The control unit is configured to detect a condition has occurred when all of the processing cores have written a value to the control unit and the control unit has turned off the respective clock signal to all of the processing cores. The control unit is configured to simultaneously turn on the respective clock signal to all of the processing cores in response to detecting the condition has occurred.

    Abstract translation: 微处理器包括控制单元，该控制单元被配置为选择性地将各个时钟信号控制到多个处理核心中的每一个。 每个处理核心被配置为分别向控制单元写入一个值。 对于所述多个处理核心的每个核心，所述控制单元被配置为响应于所述核心向所述控制单元写入值而将相应的时钟信号关断到所述核心。 控制单元被配置为检测当所有处理核心已经向控制单元写入值并且控制单元已经将各个时钟信号截止到所有处理核心时发生的状况。 控制单元被配置为响应于检测到所发生的状况，同时将各个时钟信号接通到所有处理核心。

    Processor that performs approximate computing instructions
    78.
    发明授权
    Processor that performs approximate computing instructions 有权
    执行近似计算指令的处理器

    公开(公告)号：US09389863B2

    公开(公告)日：2016-07-12

    申请号：US14522512

    申请日：2014-10-23

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker

    IPC: G06F9/30 ,  G06F11/07

    CPC classification number: G06F9/30145 ,  G06F9/30014 ,  G06F9/30076 ,  G06F9/30185 ,  G06F9/30189 ,  G06F11/0721 ,  G06F11/0793

    Abstract: A processor includes a decoder that decodes an instruction that instructs the processor to perform subsequent computations in an approximate manner and a functional unit that performs the subsequent computations in the approximate manner in response to the instruction. An instruction instructs the processor to clear an error amount associated with a value stored in a general purpose register of the processor. The error amount indicates an amount of error associated with a result of a computation performed by the processor in an approximate manner. The processor also clears the error amount in response to the instruction. Another instruction specifies a computation to be performed and includes a prefix that indicates the processor is to perform the computation in an approximate manner. The functional unit performs the computation specified by the instruction in the approximate manner specified by the prefix.

    Abstract translation: 一种处理器包括一个译码器，该解码器解码指示处理器以近似方式执行后续计算的指令，以及响应该指令以近似方式执行后续计算的功能单元。 指令指示处理器清除与存储在处理器的通用寄存器中的值相关联的错误量。 错误量表示与处理器以近似的方式执行的计算结果相关联的错误量。 处理器还会根据指令清除错误量。 另一个指令指定要执行的计算，并且包括指示处理器以近似的方式执行计算的前缀。 功能单元以由前缀指定的近似方式执行由指令指定的计算。

    Distributed management of a shared clock source to a multi-core microprocessor
    79.
    发明授权
    Distributed management of a shared clock source to a multi-core microprocessor 有权
    将共享时钟源分布式管理到多核微处理器

    公开(公告)号：US09298212B2

    公开(公告)日：2016-03-29

    申请号：US14143666

    申请日：2013-12-30

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： Darius D. Gaskins ,  G. Glenn Henry

    IPC: G06F1/06 ,  G06F1/32

    CPC classification number: G06F1/06 ,  G06F1/3296 ,  Y02D10/172

    Abstract: Microprocessors are provided with decentralized logic and associated methods for indicating power related operating states, such as desired voltages and frequency ratios, to shared microprocessor power resources such as a voltage regulator module (VRM) and phase locked loops (PLLs). Each core is configured to generate a value to indicate a desired operating state of the core. Each core is also configured to receive a corresponding value from each other core sharing the applicable resource, and to calculate a composite value compatible with the minimal needs of each core sharing the applicable resource. Each core is further configured to conditionally drive the composite value off core to the applicable resource based on whether the core is designated as a master core for purposes of controlling or coordinating the applicable resource. The composite value is supplied to the applicable shared resource without using any active logic outside the plurality of cores.

    Abstract translation: 微处理器具有分散逻辑和相关联的方法，用于将功率相关的操作状态（例如期望的电压和频率比）指示给共享的微处理器功率资源，例如电压调节器模块（VRM）和锁相环（PLL）。 每个核心被配置为产生一个值以指示所述核心的期望操作状态。 每个核心还被配置为从彼此分配可用资源的核心接收相应的值，并且计算与共享可应用资源的每个核心的最小需求兼容的复合值。 每个核心还被配置为基于是否将核心指定为主核以有条件地将核心的复合值驱动到适用的资源，以便控制或协调适用的资源。 复合值被提供给可应用的共享资源，而不使用多个核之外的任何活动逻辑。

    Apparatus and method for compression and decompression of microprocessor configuration data
    80.
    发明授权
    Apparatus and method for compression and decompression of microprocessor configuration data 有权
    用于压缩和解压缩微处理器配置数据的装置和方法

    公开(公告)号：US08982655B1

    公开(公告)日：2015-03-17

    申请号：US13972794

    申请日：2013-08-21

    Applicant: VIA Technologies, Inc.

    Inventor： G. Glenn Henry ,  Dinesh K. Jain

    IPC: G11C17/18 ,  G11C17/16

    CPC classification number: G11C17/16 ,  G06F11/1008 ,  G11C29/802

    Abstract: An apparatus is contemplated for storing and providing configuration data to a microprocessor. The apparatus has a core, disposed on a die, and a fuse array, disposed on the die and coupled to the core, where the fuse array comprises a plurality of semiconductor fuses programmed with compressed configuration data for the core, where the compressed configuration data is generated by compression of data within a virtual fuse array that corresponds to the core, and where the core accesses and decompresses the compressed configuration data upon power-up/reset, for initialization of elements within the core.

    Abstract translation: 可以预期用于存储和提供配置数据给微处理器的装置。 该设备具有设置在管芯上的核心和熔丝阵列，该熔丝阵列设置在管芯上并且耦合到核心，其中熔丝阵列包括用于核心的压缩配置数据编程的多个半导体熔丝，其中压缩的配置数据 通过对与核心对应的虚拟熔丝阵列内的数据进行压缩而产生，并且其中核心在上电/复位时对压缩的配置数据进行访问和解压缩，以用于初始化核心内的元件。

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