公开(公告)号：US20110273219A1

公开(公告)日：2011-11-10

申请号：US12775131

申请日：2010-05-06

申请人： Giulio G. Marotta ,  Carlo Musilli ,  Stefano Perugini ,  Alessandro Torsi ,  Tommaso Vali

发明人： Giulio G. Marotta ,  Carlo Musilli ,  Stefano Perugini ,  Alessandro Torsi ,  Tommaso Vali

IPC分类号： H03K17/687

CPC分类号： G11C7/12 ,  H03K3/35613 ,  H03K19/018528

摘要： Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage.

摘要翻译： 公开了电压开关，存储器件，存储器系统和用于切换的方法。 一个这样的电压开关使用串联耦合的一对开关电路，每个开关电路由电平移位电路驱动。 每个开关电路使用具有并联控制晶体管的一组串联耦合晶体管，其中每组中的晶体管数量可由每个晶体管的预期开关输入电压和最大允许电压降确定。 使能信号的特定状态的电压由电平移位电路移动到开关输入电压。 使能信号的特定状态使电压开关导通，使得开关输出电压基本上等于开关输入电压。

公开(公告)号：US07200041B2

公开(公告)日：2007-04-03

申请号：US10932489

申请日：2004-09-02

申请人： Giulio G. Marotta ,  Tommaso Vali

发明人： Giulio G. Marotta ,  Tommaso Vali

IPC分类号： G11C11/34

CPC分类号： G11C7/04 ,  G11C7/14 ,  G11C16/24 ,  G11C16/26

摘要： Single-ended sensing devices for sensing a programmed state of a floating-gate memory cell are adapted for use in low-voltage memory devices. The sensing device has an input node selectively coupled to the memory cell. The sensing device includes a precharging path for applying a precharge potential to the input node of the sensing device for precharging bit lines prior to sensing the programmed state of the memory cell, and a reference current path for applying a reference current to the input node of the sensing device. The sensing device still further includes a sense inverter having an input coupled to the input node of the sensing device and an output for providing an output signal indicative of the programmed state of the memory cell. The reference current is applied to the input node of the sensing device during sensing of the programmed state of the memory cell.

摘要翻译： 用于感测浮栅存储器单元的编程状态的单端感测装置适用于低电压存储器件。 感测装置具有选择性地耦合到存储单元的输入节点。 感测装置包括用于将预充电电位施加到感测装置的输入节点的预充电路径，用于在感测存储器单元的编程状态之前对位线进行预充电，以及用于将参考电流施加到输入节点的参考电流路径 感测装置。 感测装置还包括感测反相器，其具有耦合到感测装置的输入节点的输入和用于提供指示存储器单元的编程状态的输出信号的输出。 在感测存储器单元的编程状态期间，将参考电流施加到感测装置的输入节点。

公开(公告)号：US07164607B2

公开(公告)日：2007-01-16

申请号：US11142114

申请日：2005-06-01

申请人： Girolamo Gallo ,  Giuliano Gennaro Imondi ,  Giovanni Naso ,  Tommaso Vali

发明人： Girolamo Gallo ,  Giuliano Gennaro Imondi ,  Giovanni Naso ,  Tommaso Vali

IPC分类号： G11C7/10

CPC分类号： G11C7/106 ,  G11C7/1021 ,  G11C7/103 ,  G11C7/1051 ,  G11C7/1066

摘要： Methods and apparatus for a memory device including a burst architecture employ a double bus architecture that is multiplexed onto an output bus. The resulting architecture effectively facilitates doubling throughput without increasing memory device latency.

摘要翻译： 包括突发体系结构的存储器件的方法和装置采用复用到输出总线上的双总线架构。 所产生的架构有效地增加了吞吐量，而不会增加内存设备的延迟。

公开(公告)号：US07145799B2

公开(公告)日：2006-12-05

申请号：US11170880

申请日：2005-06-30

申请人： Giovanni Naso ,  Pietro Piersimoni ,  Tommaso Vali

发明人： Giovanni Naso ,  Pietro Piersimoni ,  Tommaso Vali

IPC分类号： G11C16/22

CPC分类号： G11C7/24 ,  G11C16/22 ,  G11C2029/4402

摘要： An improved Flash memory device is described with a protection register lock bit erase enable circuit. A bond pad coupled to the lock bit erase enable circuit of the improved Flash memory is not bonded when the individual Flash memory chip wafer is packaged. This allows the memory manufacturer to access the bond pad and erase the lock bits while the chip is still in wafer form via a test card probe, but makes the lock bits effectively uneraseable when the chip wafer is packaged. This enables the memory chip manufacturer to enhance reliability and fault tolerance of the Flash memory device by thoroughly testing the lock bits and protection register functionality. Additionally, the lock bit erase enable circuit increases manufacturing flexibility by allowing the memory chip manufacturer to reprogram the protection register and lock bits in case of organizational changes or inadvertent or erroneous programming of the protection register.

摘要翻译： 用保护寄存器锁定位擦除使能电路描述改进的闪速存储器件。 当单独的闪存芯片晶片被封装时，耦合到改进的闪速存储器的锁定位擦除使能电路的接合焊盘不被接合。 这允许存储器制造商通过测试卡探针访问焊盘并擦除锁定位，同时芯片仍然是晶片形式，但是当芯片晶片被封装时，使得锁定位有效地不可靠。 这使得内存芯片制造商能够通过彻底测试锁定位和保护寄存器功能来增强闪存设备的可靠性和容错能力。 此外，锁定位擦除使能电路通过允许存储器芯片制造商在组织改变或保护寄存器的无意或错误编程的情况下重新编程保护寄存器和锁定位来提高制造灵活性。

公开(公告)号：US07143255B2

公开(公告)日：2006-11-28

申请号：US10854397

申请日：2004-05-26

申请人： Luca De Santis ,  Tommaso Vali

发明人： Luca De Santis ,  Tommaso Vali

IPC分类号： G06F12/14

CPC分类号： G11C16/22

摘要： A chip protection register lock circuit uses a plurality of lock bits in a lock bit register. If the register contains N bits, N/2 bits of the register are coupled to an erase circuit and the remaining N/2 bits are coupled to a programming circuit. After the chip protection register is programmed, the group of N/2 bits coupled to the erase circuit are erased and the remaining N/2 bits are programmed such that an alternating pattern of logical ones and zeros are in the lock bit register. A read and compare circuit generates a lock indication if the alternating pattern is present.

摘要翻译： 芯片保护寄存器锁定电路在锁定位寄存器中使用多个锁定位。 如果寄存器包含N位，则寄存器的N / 2位耦合到擦除电路，剩余的N / 2位耦合到编程电路。 在编程芯片保护寄存器之后，擦除与擦除电路相关的N / 2位的组，并对其余的N / 2位进行编程，使得逻辑1和0的交替模式位于锁定位寄存器中。 如果存在交替模式，则读取和比较电路产生锁定指示。

公开(公告)号：US20050207233A1

公开(公告)日：2005-09-22

申请号：US11142114

申请日：2005-06-01

申请人： Girolamo Gallo ,  Giuliano Imondi ,  Giovanni Naso ,  Tommaso Vali

发明人： Girolamo Gallo ,  Giuliano Imondi ,  Giovanni Naso ,  Tommaso Vali

IPC分类号： G11C7/10 ,  G11C5/00

CPC分类号： G11C7/106 ,  G11C7/1021 ,  G11C7/103 ,  G11C7/1051 ,  G11C7/1066

摘要： Methods and apparatus for a memory device including a burst architecture employ a double bus architecture that is multiplexed onto an output bus. The resulting architecture effectively facilitates doubling throughput without increasing memory device latency.

摘要翻译： 包括突发体系结构的存储器件的方法和装置采用复用到输出总线上的双总线架构。 所产生的架构有效地增加了吞吐量，而不会增加内存设备的延迟。

公开(公告)号：US06947323B2

公开(公告)日：2005-09-20

申请号：US10698752

申请日：2003-10-31

申请人： Giovanni Naso ,  Pietro Piersimoni ,  Tommaso Vali

发明人： Giovanni Naso ,  Pietro Piersimoni ,  Tommaso Vali

IPC分类号： G11C7/24 ,  G11C16/00 ,  G11C16/04 ,  G11C16/22 ,  G11C17/00

CPC分类号： G11C7/24 ,  G11C16/22 ,  G11C2029/4402

摘要： An improved Flash memory device is described with a protection register lock bit erase enable circuit. A bond pad coupled to the lock bit erase enable circuit of the improved Flash memory is not bonded when the individual Flash memory chip wafer is packaged. This allows the memory manufacturer to access the bond pad and erase the lock bits while the chip is still in wafer form via a test card probe, but makes the lock bits effectively uneraseable when the chip wafer is packaged. This enables the memory chip manufacturer to enhance reliability and fault tolerance of the Flash memory device by thoroughly testing the lock bits and protection register functionality. Additionally, the lock bit erase enable circuit increases manufacturing flexibility by allowing the memory chip manufacturer to reprogram the protection register and lock bits in case of organizational changes or inadvertent or erroneous programming of the protection register.

摘要翻译： 用保护寄存器锁定位擦除使能电路描述改进的闪速存储器件。 当单独的闪存芯片晶片被封装时，耦合到改进的闪速存储器的锁定位擦除使能电路的接合焊盘不被接合。 这允许存储器制造商通过测试卡探针访问焊盘并擦除锁定位，同时芯片仍然是晶片形式，但是当芯片晶片被封装时，使得锁定位有效地不可靠。 这使得内存芯片制造商能够通过彻底测试锁定位和保护寄存器功能来增强闪存设备的可靠性和容错能力。 此外，锁定位擦除使能电路通过允许存储器芯片制造商在组织改变或保护寄存器的无意或错误编程的情况下重新编程保护寄存器和锁定位来提高制造灵活性。

公开(公告)号：US20180286483A1

公开(公告)日：2018-10-04

申请号：US15477048

申请日：2017-04-01

申请人： Akira Goda ,  Tommaso Vali ,  Carmine Miccoli ,  Pranav Kalavade

发明人： Akira Goda ,  Tommaso Vali ,  Carmine Miccoli ,  Pranav Kalavade

IPC分类号： G11C16/04 ,  G11C16/34 ,  G11C16/12 ,  G11C8/08

CPC分类号： G11C16/0483 ,  G11C8/08 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3459 ,  G11C2211/5621

摘要： Technology for a memory device operable to program memory cells in the memory device is described. The memory device can include a plurality of memory cells and a memory controller. The memory controller can perform a first programming pass to program a memory cell in the plurality of memory cells. A defined number of blanket programming pulses can be applied to the memory cell during the first programming pass. The blanket programming pulses may not include verify operations. The memory controller can perform a second programming pass to program the memory cell. A defined number of program and verify (PV) pulses can be applied to the memory cell during the second programming pass.

公开(公告)号：US20160093379A1

公开(公告)日：2016-03-31

申请号：US14498084

申请日：2014-09-26

申请人： Umberto Siciliani ,  Tommaso Vali ,  Terry Grunzke ,  Ali Mohammadzadeh

发明人： Umberto Siciliani ,  Tommaso Vali ,  Terry Grunzke ,  Ali Mohammadzadeh

IPC分类号： G11C16/08

CPC分类号： G11C16/08 ,  G06F12/06 ,  G06F2212/2022 ,  G11C5/066 ,  G11C7/1045 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C27/02 ,  G11C2211/5641

摘要： Technology for performing addressing in a NAND memory is described. A defined number of address cycles supported at either a memory controller or a NAND memory to address individual memory units in the NAND memory can be identified. The defined number of address cycles in which to operate can be selected in order to address the individual memory units in the NAND memory. Either the memory controller or the NAND memory can be configured to operate at the selected number of address cycles where the individual memory units in the NAND memory are uniquely addressable using a multi die select (MDS).

摘要翻译： 描述在NAND存储器中执行寻址的技术。 可以识别在存储器控制器或NAND存储器中支持的用于寻址NAND存储器中的各个存储器单元的定义数量的地址周期。 可以选择要定义的操作地址周期数，以便寻址NAND存储器中的各个存储器单元。 可以将存储器控制器或NAND存储器配置为以所选择的地址周期数进行操作，其中NAND存储器中的各个存储器单元使用多管芯选择（MDS）可唯一寻址。

公开(公告)号：US08902653B2

公开(公告)日：2014-12-02

申请号：US13208802

申请日：2011-08-12

申请人： William H. Radke ,  Tommaso Vali ,  Michele Incarnati

发明人： William H. Radke ,  Tommaso Vali ,  Michele Incarnati

IPC分类号： G11C11/34 ,  G11C16/06 ,  G06F11/10 ,  G11C16/10 ,  G11C16/04 ,  G11C11/56

CPC分类号： G06F11/1048 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0629 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/1072 ,  G06F12/0207 ,  G06F12/0646 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/52

摘要： Memory devices and methods of operating memory devices are disclosed. In one such method, different blocks of memory cells have different configurations of user data space and overhead data space. In at least one method, overhead data is distributed within more than one block of memory cells. In another method, blocks are reconfigurable responsive to particular operating modes and/or desired levels of reliability of user data stored in a memory device.

摘要翻译： 公开了存储器件和操作存储器件的方法。 在一种这样的方法中，不同的存储器单元块具有用户数据空间和开销数据空间的不同配置。 在至少一种方法中，开销数据分布在多于一个存储单元块内。 在另一种方法中，可以响应于存储在存储器设备中的特定操作模式和/或用户数据的可靠性的期望级别重新配置块。