公开(公告)号：US20130299987A1

公开(公告)日：2013-11-14

申请号：US13949631

申请日：2013-07-24

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Mei-Hsuan LIN ,  Chih-Hsun LIN ,  Chih-Kang CHAO ,  Ling-Sung WANG

IPC分类号： H01L23/48

CPC分类号： H01L23/481 ,  H01L21/76802 ,  H01L21/76822 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure includes a substrate, a conductive feature over the substrate, a conductive plug structure contacting a portion of an upper surface of the conductive feature, a first etch stop layer over another portion of the upper surface of the conductive feature, and a second etch stop layer over the first etch stop layer. The first etch stop layer is a doped etch stop layer. The first etch stop layer is to function as an etch stop layer during a predetermined etching process for etching the second etch stop layer.

摘要翻译： 半导体结构包括衬底，衬底上的导电特征，与导电特征的上表面的一部分接触的导电插塞结构，在导电特征的上表面的另一部分上的第一蚀刻停止层，以及第二 第一蚀刻停止层上的蚀刻停止层。 第一蚀刻停止层是掺杂的蚀刻停止层。 在用于蚀刻第二蚀刻停止层的预定蚀刻工艺期间，第一蚀刻停止层用作蚀刻停止层。

公开(公告)号：US08569166B2

公开(公告)日：2013-10-29

申请号：US13152865

申请日：2011-06-03

申请人： Francimar Campana Schmitt ,  Li-Qun Xia ,  Son Van Nguyen ,  Shankar Venkataraman

发明人： Francimar Campana Schmitt ,  Li-Qun Xia ,  Son Van Nguyen ,  Shankar Venkataraman

IPC分类号： H01L21/4763

CPC分类号： H01L21/76835 ,  C23C16/0272 ,  C23C16/30 ,  C23C16/325 ,  C23C16/505 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/02351 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/3121 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/7681 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832

摘要： Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer on the substrate, wherein the barrier layer comprises silicon and carbon and has a dielectric constant less than 4, depositing a dielectric initiation layer adjacent the barrier layer, and depositing a first dielectric layer adjacent the dielectric initiation layer, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less.

公开(公告)号：US20130273732A1

公开(公告)日：2013-10-17

申请号：US13915287

申请日：2013-06-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Chi KO ,  Chia Cheng CHOU ,  Keng-Chu LIN ,  Joung-Wei LIOU ,  Shwang-Ming JENG ,  Mei-Ling CHEN

IPC分类号： H01L21/768 ,  H01L21/70

CPC分类号： H01L21/768 ,  H01L21/02126 ,  H01L21/02134 ,  H01L21/02137 ,  H01L21/02203 ,  H01L21/3105 ,  H01L21/70 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76828

摘要： An Active Energy Assist (AEA) baking chamber includes an AEA light source assembly and a heater pedestal. The AEA baking chamber further includes a controller for controlling a power input to the AEA light source assembly and a power input to the heater pedestal. A method of forming interconnects on a substrate includes etching a substrate and wet cleaning the etched substrate. The method further includes active energy assist (AEA) baking the substrate after the wet-cleaning. The AEA baking includes placing the substrate on a heater pedestal in an AEA chamber, exposing the substrate to light having a wavelength equal to or greater than 400 nm, wherein said light is emitted by a light source and controlling the light source and the heater pedestal using a controller.

摘要翻译： 主动能量辅助（AEA）烘烤室包括AEA光源组件和加热器底座。 AEA烘烤室还包括控制器，用于控制输入到AEA光源组件的功率和对加热器基座的功率输入。 在衬底上形成互连的方法包括蚀刻衬底并湿式清洗蚀刻的衬底。 该方法还包括在湿清洗之后对基材进行活性能量助剂（AEA）的烘烤。 AEA烘烤包括将基板放置在AEA室中的加热器基座上，将基板暴露于等于或大于400nm的波长的光，其中所述光由光源发射并控制光源和加热器基座 使用控制器。

公开(公告)号：US08557712B1

公开(公告)日：2013-10-15

申请号：US12334726

申请日：2008-12-15

申请人： George Andrew Antonelli ,  Bart Van Schravendijk

发明人： George Andrew Antonelli ,  Bart Van Schravendijk

IPC分类号： H01L21/312

CPC分类号： C23C16/045 ,  C23C16/30 ,  C23C16/509 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/76224 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76837 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： New methods of filling gaps with dielectric material are provided. The methods involve plasma-enhanced chemical vapor deposition (PECVD) of a flowable polymerized film in a gap, followed by an in-situ treatment to convert the film to a dielectric material. According to various embodiments, the in-situ treatment may be a purely thermal or plasma treatment process. Unlike conventional PECVD processes of solid material, which deposit film in a conformal process, the deposition results in bottom-up fill of the gap. In certain embodiments, a deposition-in situ treatment-deposition-in situ treatment process is performed to form dielectric layers in the gap. The sequence is repeated as necessary for bottom up fill of the gap. Also in certain embodiments, an ex-situ post-treatment process is performed after gap fill is completed. The processes are applicable to frontend and backend gapfill.

摘要翻译： 提供了与介电材料填充间隙的新方法。 该方法涉及间隙中的可流动聚合膜的等离子体增强化学气相沉积（PECVD），随后进行原位处理以将膜转换成电介质材料。 根据各种实施方案，原位处理可以是纯热或等离子体处理方法。 不同于常规PECVD工艺的固体材料，其在保形工艺中沉积膜，沉积导致间隙的自底向上填充。 在某些实施方案中，进行沉积原位处理 - 沉积原位处理工艺以在间隙中形成介电层。 根据需要重复序列，以便自下而上填补间隙。 同样在某些实施例中，在间隙填充完成之后执行非原位后处理过程。 该过程适用于前端和后端填缝。

公开(公告)号：US08513111B2

公开(公告)日：2013-08-20

申请号：US11485078

申请日：2006-07-12

申请人： Robert P. Meagley ,  Kevin P. O'Brien ,  Tian-An Chen ,  Michael D. Goodner ,  James Powers ,  Huey-Chiang Liou

发明人： Robert P. Meagley ,  Kevin P. O'Brien ,  Tian-An Chen ,  Michael D. Goodner ,  James Powers ,  Huey-Chiang Liou

IPC分类号： H01L23/58

CPC分类号： H01L23/5222 ,  H01L21/02118 ,  H01L21/02134 ,  H01L21/02137 ,  H01L21/02164 ,  H01L21/0234 ,  H01L21/02351 ,  H01L21/312 ,  H01L21/76224 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure may be covered with a thermally decomposing film. That film may then be covered by a sealing cover. Subsequently, the thermally decomposing material may be decomposed, forming a cavity.

摘要翻译： 半导体结构可以被热分解膜覆盖。 然后该膜可以被密封盖覆盖。 随后，热分解材料可能被分解，形成空腔。

公开(公告)号：US08449787B2

公开(公告)日：2013-05-28

申请号：US12035832

申请日：2008-02-22

申请人： Tadahiro Imada ,  Yoshihiro Nakata ,  Koji Nozaki

发明人： Tadahiro Imada ,  Yoshihiro Nakata ,  Koji Nozaki

IPC分类号： C03C15/00

CPC分类号： H01L21/67086 ,  H01L21/31111 ,  H01L21/31133 ,  H01L21/3143 ,  H01L21/31612 ,  H01L21/31633 ,  H01L21/6708 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76825

摘要： A wet etching method that includes forming an insulating film on a substrate, and irradiating laser light to the insulating film during wet etching of the insulating film using an etching solution.

摘要翻译： 一种湿式蚀刻方法，其包括在基板上形成绝缘膜，并且在使用蚀刻溶液湿式蚀刻绝缘膜期间，将绝缘膜照射激光。

公开(公告)号：US08415248B2

公开(公告)日：2013-04-09

申请号：US13474349

申请日：2012-05-17

申请人： Shyng-Tsong Chen ,  Qinghuang Lin ,  Sampath Purushothaman ,  Terry A. Spooner ,  Shawn M. Walsh

发明人： Shyng-Tsong Chen ,  Qinghuang Lin ,  Sampath Purushothaman ,  Terry A. Spooner ,  Shawn M. Walsh

IPC分类号： H01L21/4763

CPC分类号： H01L23/5329 ,  H01L21/4846 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76831 ,  H01L23/49894 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A self-aligned interconnect structure is provided that includes a first patterned and cured low-k material located on a surface of a substrate, wherein the first patterned and cured low-k material includes at least one first interconnect pattern (via or trench pattern) therein. A second patterned and cured low-k material having at least one second interconnect pattern that is different from the first interconnect pattern is located atop the first patterned and cured low k material. A portion of the second patterned and cured low-k material partially fills the at least one first interconnect within the first patterned and cured low-k material. A conductive material fills the at least one first interconnect pattern and the at least one second interconnect pattern. A method of forming such a self-aligned interconnect structure is also provided.

摘要翻译： 提供了自对准的互连结构，其包括位于衬底的表面上的第一图案化和固化的低k材料，其中第一图案化和固化的低k材料包括至少一个第一互连图案（通孔或沟槽图案） 其中。 具有不同于第一互连图案的至少一个第二互连图案的第二图案化和固化的低k材料位于第一图案化和固化的低k材料的顶部。 第二图案化和固化的低k材料的一部分部分地填充第一图案化和固化的低k材料内的至少一个第一互连。 导电材料填充至少一个第一互连图案和至少一个第二互连图案。 还提供了形成这种自对准互连结构的方法。

公开(公告)号：US08390099B2

公开(公告)日：2013-03-05

申请号：US12862140

申请日：2010-08-24

申请人： Shirou Ozaki ,  Yoshihiro Nakata ,  Tadahiro Imada ,  Yasushi Kobayashi

发明人： Shirou Ozaki ,  Yoshihiro Nakata ,  Tadahiro Imada ,  Yasushi Kobayashi

IPC分类号： H01L23/58

CPC分类号： H01L23/5329 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/3121 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76829 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/31663 ,  H01L2924/00

摘要： An interconnection substrate including: a first insulating film made of a silicon compound, an adhesion enhancing layer formed on the first insulating film, and a second insulting film made of a silicon compound and formed on the adhesion enhancing layer, wherein the first insulating film and the second insulating film are combined together with a component having a structure represented by General Formula (1) described below: Si—CXHY—Si  General Formula (1) where y is equal to 2x and is an even integer.

摘要翻译： 一种互连基板，包括：由硅化合物制成的第一绝缘膜，形成在第一绝缘膜上的粘合增强层和形成在粘合增强层上的由硅化合物制成的第二绝缘膜，其中第一绝缘膜和 第二绝缘膜与具有下述通式（1）所示结构的成分组合在一起：Si-CXHY-Si通式（1），其中y等于2×并且是偶数整数。

公开(公告)号：US20130043590A1

公开(公告)日：2013-02-21

申请号：US13212469

申请日：2011-08-18

申请人： Mei-Hsuan LIN ,  Chih-Hsun LIN ,  Chih-Kang CHAO ,  Ling-Sung WANG

发明人： Mei-Hsuan LIN ,  Chih-Hsun LIN ,  Chih-Kang CHAO ,  Ling-Sung WANG

IPC分类号： H01L21/768 ,  H01L23/48

CPC分类号： H01L23/481 ,  H01L21/76802 ,  H01L21/76822 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present application discloses a method of manufacturing a semiconductor structure. According to at least one embodiment, a first etch stop layer is formed over a conductive feature and a substrate, and the conductive feature is positioned over the substrate. A second etch stop layer is formed over the first etch stop layer. A first etch is performed to form an opening in the second etch stop layer, and the opening exposes a portion of the first etch stop layer. A second etch is performed to extend the opening downwardly by removing a portion of the exposed first etch stop layer, and the extended opening exposes a portion of the conductive feature.

摘要翻译： 本申请公开了一种制造半导体结构的方法。 根据至少一个实施例，在导电特征和衬底之上形成第一蚀刻停止层，并且导电特征位于衬底上。 在第一蚀刻停止层上形成第二蚀刻停止层。 执行第一蚀刻以在第二蚀刻停止层中形成开口，并且开口暴露第一蚀刻停止层的一部分。 执行第二蚀刻以通过去除暴露的第一蚀刻停止层的一部分向下延伸开口，并且延伸的开口暴露导电特征的一部分。

公开(公告)号：US20130001781A1

公开(公告)日：2013-01-03

申请号：US13602126

申请日：2012-09-01

申请人： Maxime Darnon ,  Qinghuang Lin

发明人： Maxime Darnon ,  Qinghuang Lin

IPC分类号： H01L23/532 ,  H01L23/522

CPC分类号： H01L21/76804 ,  C08G77/04 ,  H01L21/02126 ,  H01L21/02318 ,  H01L21/31 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： An interconnect structure is provided which includes at least one patterned and cured low-k material located directly on a surface of a substrate; and at least one least one conductively filled region embedded within an interconnect pattern located within the at least one patterned and cured low-k material, wherein the at least one conductively filled region has an inflection point at a lower region of the interconnect pattern that is in proximity to an upper surface of the substrate and the interconnect region having an upper region that has substantially straight sidewalls.

摘要翻译： 提供了一种互连结构，其包括直接位于衬底的表面上的至少一个图案化和固化的低k材料; 以及至少一个导电填充区域，其嵌入位于所述至少一个图案化和固化的低k材料内的互连图案内，其中所述至少一个导电填充区域在所述互连图案的下部区域具有拐点， 靠近衬底的上表面，并且互连区域具有具有基本上直的侧壁的上部区域。