公开(公告)号：US20020003694A1

公开(公告)日：2002-01-10

申请号：US09944232

申请日：2001-08-30

Inventor： Larry D. Kinsman ,  Jerry M. Brooks ,  Walter L. Moden

IPC: H05K007/20

CPC classification number: H05K3/303 ,  H01L23/3675 ,  H01L23/4334 ,  H01L2924/0002 ,  H05K1/0203 ,  H05K2201/09709 ,  H05K2201/10454 ,  H05K2201/10659 ,  H05K2201/10696 ,  Y02P70/613 ,  H01L2924/00

Abstract: A high density vertical surface mount package and thermal carrier therefor including a heat sink.

Abstract translation: 一种高密度垂直表面贴装封装及其热载体，包括散热片

公开(公告)号：US06330158B1

公开(公告)日：2001-12-11

申请号：US09587610

申请日：2000-06-05

Applicant: Salman Akram

Inventor： Salman Akram

IPC: H05K720

CPC classification number: H01L24/73 ,  H01L23/4334 ,  H01L23/4951 ,  H01L24/29 ,  H01L24/33 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/83805 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01055 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/15763 ,  H01L2924/181 ,  H05K1/18 ,  H05K2201/10151 ,  H05K2201/10454 ,  H05K2201/10522 ,  H05K2201/10696 ,  H01L2924/01014 ,  H01L2924/01079 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/01032 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/0665 ,  H01L2924/0695 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor package includes a semiconductor die, a lead frame wire bonded to the die, and a plastic body encapsulating the die. The package also includes a first heat sink attached to a face of the die, and a second heat sink attached to a back side of the die. Thermally conductive adhesive layers attach the heat sinks to the die, and provide a thermal path therebetween. In addition, the heat sinks project from the plastic body, and have end portions that are sized and shaped to interlock with heat sinks on an adjacent package to form an electronic assembly. In the electronic assembly, the interlocking heat sinks maintain contact surfaces on the heat sinks in physical contact and improve heat dissipation from the packages. An alternate embodiment package includes a thermally conductive encapsulant which attaches a pair of heat sinks, and encapsulates the die.

Abstract translation: 半导体封装包括半导体管芯，结合到管芯的引线框架引线和封装管芯的塑料体。 该包装还包括附接到模具的表面的第一散热器和附接到模具的背面的第二散热器。 导热粘合剂层将散热器附接到模具，并且在它们之间提供热路径。 此外，散热器从塑料体突出，并且具有尺寸和形状的端部，以与相邻封装上的散热器互锁以形成电子组件。 在电子组件中，互锁散热器保持物理接触的散热器上的接触表面并改善封装的散热。 替代实施例包装包括附接一对散热器并封装管芯的导热密封剂。

公开(公告)号：US20010011762A1

公开(公告)日：2001-08-09

申请号：US09819874

申请日：2001-03-28

Inventor： David J. Corisis ,  Tracy Reynolds ,  Michael Slaughter ,  Daniel Cram ,  Leland R. Nevill ,  Jerrold L. King

IPC: H01L023/495 ,  H01L023/48 ,  H01L023/52 ,  H01L023/28

CPC classification number: G01R31/2851 ,  G01R1/0408 ,  G01R31/2884 ,  H01L23/4951 ,  H01L23/544 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/303 ,  H05K2201/10568 ,  H05K2201/10689 ,  H05K2201/10696 ,  H05K2203/167 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: An integrated circuit is provided having an alignment feature integral with the lead frame. The integrated circuit includes a lead frame coupled with a semiconductor die, and is partially encapsulated in insulating material. The lead frame has the alignment feature therein. The alignment feature includes a cut out on the lead frame taking the form of a semi-circle, protuberance, apertures, or slots. Alternatively, the alignment feature includes a removably coupled tab. After testing of the integrated circuit has been completed, the alignment tab is removed from the integrated circuit. The alignment feature can also be provided on a heat spreader which is attached to a side of or within the lead frame package.

Abstract translation: 提供了具有与引线框一体的对准特征的集成电路。 集成电路包括与半导体管芯耦合的引线框架，并部分封装在绝缘材料中。 引线框架具有其中的对准特征。 对准特征包括在引线框架上切割成半圆形，突起，孔或槽的形式。 或者，对准特征包括可移除地耦合的突片。 集成电路测试完成后，对准标签从集成电路中取出。 对准特征也可以设置在附着于引线框架封装的一侧或内部的散热器上。

公开(公告)号：US06246108B1

公开(公告)日：2001-06-12

申请号：US09374176

申请日：1999-08-12

Applicant: David J. Corisis ,  Tracy Reynolds ,  Michael Slaughter ,  Daniel Cram ,  Leland R. Nevill ,  Jerrold L. King

Inventor： David J. Corisis ,  Tracy Reynolds ,  Michael Slaughter ,  Daniel Cram ,  Leland R. Nevill ,  Jerrold L. King

IPC: H01L2348

CPC classification number: G01R31/2851 ,  G01R1/0408 ,  G01R31/2884 ,  H01L23/4951 ,  H01L23/544 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/303 ,  H05K2201/10568 ,  H05K2201/10689 ,  H05K2201/10696 ,  H05K2203/167 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: An integrated circuit is provided having an alignment feature integral with the lead frame. The integrated circuit includes a lead frame coupled with a semiconductor die, and is partially encapsulated in insulating material. The lead frame has the alignment feature therein. The alignment feature includes a cut out on the lead frame taking the form of a semi-circle, protuberance, apertures, or slots. Alternatively, the alignment feature includes a removably coupled tab. After testing of the integrated circuit has been completed, the alignment tab is removed from the integrated circuit. The alignment feature can also be provided on a heat spreader which is attached to a side of or within the lead frame package.

Abstract translation: 提供了具有与引线框一体的对准特征的集成电路。 集成电路包括与半导体管芯耦合的引线框架，并部分封装在绝缘材料中。 引线框架具有其中的对准特征。 对准特征包括在引线框架上切割成半圆形，突起，孔或槽的形式。 或者，对准特征包括可移除地耦合的突片。 集成电路测试完成后，对准标签从集成电路中取出。 对准特征也可以设置在附着于引线框架封装的一侧或内部的散热器上。

公开(公告)号：US6048744A

公开(公告)日：2000-04-11

申请号：US929843

申请日：1997-09-15

Applicant: David J. Corisis ,  Tracy Reynolds ,  Michael Slaughter ,  Daniel Cram ,  Leland R. Nevill ,  Jerrold L. King

Inventor： David J. Corisis ,  Tracy Reynolds ,  Michael Slaughter ,  Daniel Cram ,  Leland R. Nevill ,  Jerrold L. King

IPC: G01R1/04 ,  G01R31/28 ,  H01L23/495 ,  H01L23/544 ,  H05K3/30 ,  G01R31/26 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/66

CPC classification number: G01R31/2851 ,  H01L23/4951 ,  H01L23/544 ,  H05K3/303 ,  G01R1/0408 ,  G01R31/2884 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H05K2201/10568 ,  H05K2201/10689 ,  H05K2201/10696 ,  H05K2203/167 ,  Y02P70/613

Abstract: An integrated circuit is provided having an alignment feature integral with the lead frame. The integrated circuit includes a lead frame coupled with a semiconductor die, and is partially encapsulated in insulating material. The lead frame has the alignment feature therein. The alignment feature includes a cut out on the lead frame taking the form of a semi-circle, protuberance, apertures, or slots. Alternatively, the alignment feature includes a removably coupled tab. After testing of the integrated circuit has been completed, the alignment tab is removed from the integrated circuit. The alignment feature can also be provided on a heat spreader which is attached to a side of or within the lead frame package.

Abstract translation: 提供了具有与引线框一体的对准特征的集成电路。 集成电路包括与半导体管芯耦合的引线框架，并部分封装在绝缘材料中。 引线框架具有其中的对准特征。 对准特征包括在引线框架上切割成半圆形，突起，孔或槽的形式。 或者，对准特征包括可移除地耦合的突片。 集成电路测试完成后，对准标签从集成电路中取出。 对准特征也可以设置在附着于引线框架封装的一侧或内部的散热器上。

公开(公告)号：US5728601A

公开(公告)日：1998-03-17

申请号：US441595

申请日：1995-05-15

Applicant: Mitsutaka Sato ,  Masanori Yoshimoto

Inventor： Mitsutaka Sato ,  Masanori Yoshimoto

IPC: H01L23/28 ,  H01L23/31 ,  H01L23/495 ,  H01L23/50 ,  H01L25/10 ,  H05K1/18 ,  H05K3/30 ,  H01L21/56 ,  H01L21/58 ,  H01L21/60

CPC classification number: H01L23/3107 ,  H01L23/49555 ,  H01L25/105 ,  H05K3/301 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01079 ,  H05K1/181 ,  H05K2201/10454 ,  H05K2201/10606 ,  H05K2201/10696

Abstract: A process for manufacturing semiconductor package of a single in-line type including a semiconductor chip, a package body for accommodating the semiconductor chip and a plurality of leads held by the package body to extend substantially perpendicularly to a bottom edge surface of the package body. The package body carries a cutout part at a predetermined position of a side edge that surrounds the package body such that the cutout part is adapted for engagement with a support leg for supporting the package body substantially upright on a substrate.

Abstract translation: 一种用于制造包括半导体芯片，用于容纳半导体芯片的封装主体和由封装体保持的多个引线的单个直列式的半导体封装的工艺，其基本上垂直于封装体的底部边缘表面延伸。 包装体在围绕包装主体的侧边缘的预定位置处携带切口部分，使得切口部分适于与用于将包装体基本上直立支撑在基板上的支撑腿接合。

公开(公告)号：US5671125A

公开(公告)日：1997-09-23

申请号：US517308

申请日：1995-08-21

Applicant: Ernest Russell ,  Daniel Baudouin ,  James S. Wallace

Inventor： Ernest Russell ,  Daniel Baudouin ,  James S. Wallace

IPC: H01L23/32 ,  H01L23/495 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/30 ,  H05K7/02 ,  H05K1/16

CPC classification number: H05K1/181 ,  H01L23/32 ,  H01L23/49555 ,  H01L25/105 ,  H05K3/303 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2225/1082 ,  H01L2924/0002 ,  H05K2201/10454 ,  H05K2201/10545 ,  H05K2201/10568 ,  H05K2201/10659 ,  H05K2201/10696 ,  H05K2203/167 ,  Y02P70/611 ,  Y02P70/613

Abstract: Two flat packages (110, 111) are arranged to achieve a mirrored footprint by employing guides (100), which are positioned within a mounting aperature a printed circuit board. The flat packages include leads (120, 121) which extend from an edge of the flat package. A semiconductor chip is encapsulated by the flat packages.

Abstract translation: 布置两个扁平封装（110,111）以通过使用位于印刷电路板的安装温度内的引导件（100）来实现镜像覆盖。 扁平封装包括从扁平封装的边缘延伸的引线（120,121）。 半导体芯片由扁平封装封装。

公开(公告)号：US5663105A

公开(公告)日：1997-09-02

申请号：US586366

申请日：1996-01-16

Applicant: Goh Jing Sua ,  Chan Min Yu

Inventor： Goh Jing Sua ,  Chan Min Yu

IPC: H01L25/10 ,  H05K3/30 ,  H05K3/32 ,  H01L21/60

CPC classification number: H05K3/303 ,  H01L25/105 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/0002 ,  H05K2201/10454 ,  H05K2201/10537 ,  H05K2201/10696 ,  H05K3/325 ,  Y02P70/613 ,  Y10T29/4913

Abstract: The invention is to an array of stacked devices utilizing vertical surface mounted semiconductor devices stacked side by side and inserting the stack of devices into a casing. The packaged stack of devices creates a cube package which is capable of replacing SIMM boards, and saves considerable space. The casing dissipates heat generated in the devices, and may be of metal or thermally conductive plastic.

公开(公告)号：US5635760A

公开(公告)日：1997-06-03

申请号：US697604

申请日：1996-08-27

Applicant: Toru Ishikawa

Inventor： Toru Ishikawa

IPC: H01L23/50 ,  H01L23/31 ,  H01L23/495 ,  H01L25/10 ,  H05K1/18 ,  H05K3/30 ,  H05K3/34 ,  H01L23/28

CPC classification number: H01L23/3107 ,  H01L23/49555 ,  H01L25/105 ,  H05K1/181 ,  H05K3/303 ,  H01L2224/48247 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H05K2201/09954 ,  H05K2201/10454 ,  H05K2201/10462 ,  H05K2201/10522 ,  H05K2201/10568 ,  H05K2201/10689 ,  H05K2201/10696 ,  H05K3/3421 ,  Y02P70/611 ,  Y02P70/613

Abstract: A semiconductor device of the present invention includes a plurality of lead terminals extending from only one side surface of a package main body having major surfaces and side surfaces, the lead terminal extending parallel to the major surface by a predetermined size and being substantially perpendicularly bent to project from the major surface by a predetermined size in a vertical mount type semiconductor device, or being substantially perpendicularly bent to project from the major surface by a predetermined size and bent again at a distal end portion in parallel to the major surface in a horizontal mount type semiconductor device, and a supporting means projecting from the package main body by substantially the same size as the projecting size of the lead terminals. A method of manufacturing the semiconductor device of the present invention includes the steps of lead frame formation, chip mounting and bonding, mold sealing, and lead terminal formation.

Abstract translation: 本发明的半导体器件包括从仅具有主表面和侧表面的封装主体的仅一个侧表面延伸的多个引线端子，引线端子平行于主表面延伸预定尺寸并基本上垂直弯曲成 在垂直安装型半导体器件中从主表面突出预定尺寸，或者基本上垂直弯曲以从主表面突出预定尺寸，并且在水平安装件中平行于主表面的远端部分再次弯曲 以及从封装主体以与引线端子的突出尺寸大致相同的尺寸突出的支撑装置。 本发明的半导体器件的制造方法包括引线框架形成，芯片安装和接合，模具密封和引线端子形成的步骤。

公开(公告)号：US5555488A

公开(公告)日：1996-09-10

申请号：US6899

申请日：1993-01-21

Applicant: Robert N. McLellan ,  Anthony M. Chiu

Inventor： Robert N. McLellan ,  Anthony M. Chiu

IPC: H01L21/60 ,  H01L23/28 ,  H01L23/495 ,  H05K3/30 ,  H05K7/02 ,  H01L23/544

CPC classification number: H05K3/301 ,  H01L23/49555 ,  H05K3/303 ,  H01L2924/0002 ,  H05K2201/10454 ,  H05K2201/10568 ,  H05K2201/10696 ,  H05K2203/167 ,  Y02P70/613 ,  Y10T29/49121 ,  Y10T29/49139

Abstract: An electronic device (10) includes a package (16) having two posts (30) suitable for insertion in PCB holes. Package (16) presents a lengthwise molding plane (32) along which the upper portion (42) and bottom portion (44) of package (16) are mated during the molding process. Posts (30) are disposed substantially exclusively in bottom portion (44) so that posts (30) are asymmetric about lengthwise molding plane (32). Thus, even if a top mold (42a) and a bottom mold (44a) are misaligned there will be no effect on the dimensional tolerance of posts (30) and thus the tolerance of post (30) can be closely matched with a PCB hole (20) tolerance to insure a snug fit. Thus, device (10) is mounted edgewise on a PCB (18) by insertion of posts (30) into PCB holes (20) so that tips (24) of lead fingers (4 14) can be connected to PCB (18) by surfacing-mounting techniques or the like.

Abstract translation: 电子设备（10）包括具有适于插入PCB孔中的两个柱（30）的封装（16）。 包装件（16）呈现纵向成型平面（32），在模制过程中，包装件（16）的上部分（42）和底部部分（44）沿着该成型平面配合。 柱（30）基本上仅设置在底部（44）中，使得柱（30）在纵向成型平面（32）上是不对称的。 因此，即使顶模（42a）和底模（44a）不对准，也不会影响柱（30）的尺寸公差，因此柱（30）的公差可以与PCB孔 （20）公差，以确保贴合。 因此，装置（10）通过将柱（30）插入PCB孔（20）而沿PCB方式安装在PCB（18）上，使得引线指（4,14）的尖端（24）可以通过 表面贴装技术等。