公开(公告)号：US3808058A

公开(公告)日：1974-04-30

申请号：US28129572

申请日：1972-08-17

申请人： BELL TELEPHONE LABOR INC

发明人： HENNING S

IPC分类号： H01L29/73 ,  H01L21/00 ,  H01L21/329 ,  H01L21/331 ,  H01L29/00 ,  H01L7/54

CPC分类号： H01L21/00 ,  H01L29/00 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/106 ,  Y10S148/113 ,  Y10S148/114

摘要： A semiconductor diode of the mesa type having a channel guard zone is made by using a silicon nitride etch mask for the mesa etching step. As a result of the mesa etching, the silicon nitride mask is undercut leaving an overhang which then is utilized as a shadow mask for an ion implantation step. The ion implantation step produces a channel guard zone which, because of the mask overhang, is spaced away from the exposed edge of the diffused P-N junction in the mesa.

摘要翻译： 通过使用用于台面蚀刻步骤的氮化硅蚀刻掩模来制造具有沟道保护区的台面型半导体二极管。 作为台面蚀刻的结果，氮化硅掩模被切下，留下悬垂，然后用作离子注入步骤的荫罩。 离子注入步骤产生通道保护区，由于掩模突出端，其与台面中扩散的P-N结的暴露边缘间隔开。

公开(公告)号：US3787710A

公开(公告)日：1974-01-22

申请号：US3787710D

申请日：1972-01-25

申请人： CUNNINGHAM J

发明人： CUNNINGHAM J

IPC分类号： H01L21/00 ,  H01L21/762 ,  H01L23/522 ,  H01L27/00 ,  H01L19/00

CPC分类号： H01L23/522 ,  H01L21/00 ,  H01L21/76264 ,  H01L21/76289 ,  H01L24/05 ,  H01L27/00 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2924/14 ,  Y10S148/051 ,  Y10S148/085 ,  H01L2924/00

摘要： A method of fabricating an integrated circuit having interconnected circuit components adjacent one surface of a semiconductor body having its opposite surface disposed upon an insulating layer on a substrate wherein the semiconductor material between the circuit elements is removed to form a moat or channel between the circuit elements and electrically isolate them from one another by the space remaining after the removal and the insulating layer.

摘要翻译： 一种制造集成电路的方法，该集成电路具有邻近半导体本体的一个表面的互连电路部件，该半导体本体的表面设置在基板上的绝缘层上，其中，电路元件之间的半导体材料被去除以在电路元件之间形成护城河或通道 并且通过除去之后剩余的空间和绝缘层将它们彼此电隔离。

公开(公告)号：US3787253A

公开(公告)日：1974-01-22

申请号：US3787253D

申请日：1971-12-17

申请人： IBM

发明人： ASHAR K

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/74 ,  H01L21/761 ,  H01L27/00 ,  H01L7/36 ,  H01L19/00

CPC分类号： H01L21/761 ,  H01L21/74 ,  H01L27/00 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/151

摘要： An improved self-isolated semiconductor integrated circuit structure is formed by a novel process beginning with diffusing a plurality of N-type buried layers onto a P-type substrate and epitaxially growing a thin P-type layer over the surface of the P-type substrate. Base regions are formed by diffusing a plurality of P-type regions into the P-type epitaxial layer. Collector contact regions and emitter regions are formed by simultaneously diffusing a plurality of N-type regions into the P-type epitaxial layer, the collector contact regions being spaced from the P-type base region and diffused through the epitaxial layer to contact the N-type buried layer, and the emitter regions being diffused within the P-type base regions. A semiconductor integrated circuit structure results having base regions with controllable wide range concentration levels, formed with only three selective diffusion process steps.

摘要翻译： 通过一种新的工艺形成改进的自隔离半导体集成电路结构，其开始于将多个N型掩埋层扩散到P型衬底上，并在P型衬底的表面上外延生长薄P型层 。 通过将多个P型区域扩散到P型外延层中而形成基极区域。 通过将多个N型区域同时扩散到P型外延层中形成集电极接触区域和发射极区域，集电极接触区域与P型基极区域间隔开并且通过外延层扩散以接触N型区域， 型掩埋层，并且发射极区域在P型基极区域内扩散。 半导体集成电路结构具有具有可控宽范围浓度水平的基区，仅形成三个选择性扩散处理步骤。

公开(公告)号：US3783047A

公开(公告)日：1974-01-01

申请号：US3783047D

申请日：1972-03-01

申请人： PHILIPS CORP

发明人： PAFFEN M ,  APPELS J ,  VERKUIJLEN W ,  KOOI E

IPC分类号： H01L29/73 ,  H01L21/00 ,  H01L21/033 ,  H01L21/306 ,  H01L21/316 ,  H01L21/32 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L23/29 ,  H01L27/00 ,  H01L29/78 ,  H01L7/34

CPC分类号： H01L23/29 ,  H01L21/00 ,  H01L21/033 ,  H01L21/32 ,  H01L21/76 ,  H01L21/762 ,  H01L21/76216 ,  H01L27/00 ,  H01L2924/0002 ,  Y10S148/043 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/106 ,  Y10S148/113 ,  Y10S148/114 ,  Y10S148/151 ,  Y10S438/911 ,  H01L2924/00

摘要： A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE. BY USING A DOUBLE LAYER AS A MASKING LAYER, THE ELECTRIC PROPERIES OF TWO REGIONS WHICH ARE SITUATED IN THE SEMICONDUCTOR BODY ACCURATELY RELATIVE TO EACH OTHER CAN BE VARIED WITHOUT AN INTERIM PROCESION PHOTOMASKING STEP. THE INVENTION PROVIDES VWERY WIDE POSSIBILITIES OF APPLICATION. FOR EXAMPLE, THE FIRST REGION CAN BE DOPED WITH AN IMPURITY VIA AN APERATUS IN THE MASKING LAYER, AFTER WHICH THE LOWER COMPONENT LAYER OF THE MASKING LAYER IS UNDERETCHED AND AN IMPURITY IS THEN INTRODUCED INTO THE SECOND REGION. IT IS ALSO POSSIBLE, AFTER UNDERTCHING THE LOWER COMPONENT LAYER, TO OXIDISE THE SECOND REGION OF THE SEMICONDUCTOR BODY, AS A RESULT OF WHICH MAY IMPORTANT STRUCTURES ARE OBTAINED IN A SIMPLE MANNER.

公开(公告)号：US3783046A

公开(公告)日：1974-01-01

申请号：US3783046D

申请日：1971-04-22

申请人： MOTOROLA INC

发明人： MYERS C

IPC分类号： H01L21/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/485 ,  H01L7/34

CPC分类号： H01L23/3157 ,  H01L21/00 ,  H01L23/291 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S148/043 ,  Y10S148/085 ,  H01L2924/00

摘要： A SHALLOW JUNCTION, HIGH-SPEED SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME WHEREIN A FIRST OR BASE REGION OF ONE CONDUCTIVITY TYPE IS FORMED A SEMICONDUCTOR BODY USING PHOTOLITHOGRAPHIC PROCESS. MEXT, ONE OR MORE OXIDE LAYERS ARE VAPOR DEPOSITED AT A RELATIVELY LOW TEMPERATURE ON THE SURFACE OF THE STRUCTURE. AN OPENING IS THEN MADE IN THE VAPOR DEPOSITED OXIDE LAYERS TO PERMIT THE PASSAGE OF AN IMPURITY THERETHROUGH AND FORMS A SECOND, OPPOSITE CONDUCTIVITY TYPE EMITTER REGION WITHIN THE FIRST REGION. NEXT, A THIN LAYER OF OXIDE IS THERMALLY GROWN OVER THE EXPOSED PORTION OF THE BASE REGION AND OVER THE EXPOSED SURFACE OF THE VAPOR DEPOSITED OXIDE LAYERS. THEREAFTER, ONE OR MORE OPENINGS IN THE SURFACE OXIDE ARE SELECTIVELY MADE TO PERMIT THE FORMATION OF ELECTRICAL CONTACTS TO THE TRANSISTOR BASE REGION AND TO OTHER LIKE CONDUCTIVITY TYPE REGIONS IN THE SEMICONDUCTOR STRUCTURE. THEN, BY CONTROLLABLY ETCHING THE THIN THERMALLY GROWN OXIDE LAYER COVERING THE SECOND OR EMITTER REGION, THE EMITTER REGION CAN BE EXPOSED FOR THE PURPOSE OF MAKING OHMIC CONTACT THERETO. ACCORDING TO THE PRESENT PROCESS, THE THIN LAYER OF THERMALLY GROWN OXIDE IS "WASHED OUT" OF THE EMITTER REGION BY CONTROLLED ETCHING. SUCH CONTROLLED ETCHING ELIMINATES A CRITICAL MASKING STEP WHICH OTHERWISE WOULD HAVE BEEN REQUIRED TO MAKE A CONTACT OPENING FOR THE EMITTER REGION. OHMIC CONTACTS CAN NOW BE MADE TO THE BASE AND EMITTER REGIONS OF THE STRUCTURE USING CONVENTIONAL TECHNIQUES SUCH AS THE EVAPORATION OF ALUMINUM. SINCE ALL OXIDE MASKING IS REMOVED AFTER THE FORMATION OF THE BASE REGION, THE FINAL OXIDE MASKING ON THE SURFACE OF THE STRUCTURE IS OF ONE UNIFORM THICKNESS.

公开(公告)号：US3776788A

公开(公告)日：1973-12-04

申请号：US3776788D

申请日：1971-03-22

申请人： SIEMENS AG

发明人： HENKER H

IPC分类号： H01L21/00 ,  H01L21/762 ,  H01L7/50

CPC分类号： H01L21/76297 ,  H01L21/00 ,  Y10S148/026 ,  Y10S148/049 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/097 ,  Y10S148/135 ,  Y10S438/924 ,  Y10S438/928

摘要： A process for producing insulated semiconductor regions. To produce an insulated region on a semiconductor wafer, a semiconductor substrate of one conductance type is etched to the region of opposite conductance type. The etching process stops at the pn-junction. The polycrystalline semiconductor layer is separated by the etchant through an insulating layer. The invention is particularly suitable for the production of multiple structures in a semiconductor wafer.

摘要翻译： 一种绝缘半导体区域的制造方法。 为了在半导体晶片上制造绝缘区域，将一种导电型半导体衬底蚀刻到相反电导型的区域。 蚀刻过程在pn结处停止。 多晶半导体层由蚀刻剂通过绝缘层分离。 本发明特别适用于在半导体晶片中制造多个结构。

公开(公告)号：US3769105A

公开(公告)日：1973-10-30

申请号：US3769105D

申请日：1971-04-12

申请人： IBM

发明人： CHEN C ,  DHAKA V ,  KROLIKOWSKI W

IPC分类号： H01L27/07 ,  H01L7/36 ,  H01L19/00

CPC分类号： H01L27/0794 ,  H01L27/0755 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/145 ,  Y10S148/151 ,  Y10S438/901

摘要： An integrated circuit and process for making it wherein a decoupling capacitor is provided beneath devices in the surface of the integrated circuit by the formation of a first epitaxial layer between an N substrate having a P zone diffused therein and an N device-containing epitaxial layer. A P channel diffusion to the P zone formed in the substrate will serve as a damping resistor in combination with the coupling capacitor. The process for forming such a decoupling capacitor in an integrated circuit comprises, inter alia, diffusing P impurities into the substrate to form a large junction which will subsequently function as a decoupling capacitor. A first intrinsic, P or N epitaxial layer is then grown on the semiconductor substrate. Subsequently, an N epitaxial layer is grown on the first epitaxial layer. A P channel is then driven through the N epitaxial layer and the first epitaxial layer to contact the P diffused zone which serves as the decoupling capacitor. This P channel diffusion will serve as a damping resistor in combination with the decoupling capacitor. Device diffusion, i.e., transistors, resistors, etc., will take place into the N epitaxial layer, and during growth of the epitaxial layers the P zone will significantly outdiffuse into the first epitaxial layer. Appropriate channels, isolations and contacts are also provided.

摘要翻译： 一种用于制造其的集成电路和工艺，其中在集成电路的表面中的器件下方提供去耦电容器，该第一外延层在扩散在其中的P +区之间形成第一外延层，N + 含有器件的外延层。 在衬底中形成的P +区的P +沟道扩散将用作与耦合电容器组合的阻尼电阻器。 在集成电路中形成这种去耦电容器的过程尤其包括将P +杂质扩散到衬底中以形成随后用作去耦电容器的大结。 然后在半导体衬底上生长第一固有的P +或N - 外延层。 随后，在第一外延层上生长N +外延层。 然后通过N +外延层和第一外延层驱动P +沟道以接触用作去耦电容器的P +扩散区。 该P +通道扩散将与去耦电容器一起用作阻尼电阻器。 器件扩散，即晶体管，电阻器等将发生到N +外延层中，并且在外延层生长期间，P +区将显着地超出第一外延层的扩散。 还提供了适当的通道，隔离和触点。

公开(公告)号：US3765747A

公开(公告)日：1973-10-16

申请号：US3765747D

申请日：1971-08-02

申请人： TEXAS INSTRUMENTS INC

发明人： BEAN K ,  PANKRATZ J

IPC分类号： G09G3/18 ,  G02F1/136 ,  G02F1/1362 ,  G09F9/30 ,  G09F9/35 ,  G02F1/34

CPC分类号： G02F1/136277 ,  Y10S148/049 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/115 ,  Y10S148/145 ,  Y10S438/978

摘要： A liquid crystal display device having at least one of the electrodes formed within a semiconductor substrate is provided. Driver circuitry is integral with the substrate and may be formed either on the front or back side thereof. Very accurate spacing of the electrodes for the liquid crystal display is provided by forming a moat in the semiconductor substrate using an orientation dependent etch, the depth of the moat determining the electrode spacing.

摘要翻译： 提供一种液晶显示装置，其具有形成在半导体基板内的至少一个电极。 驱动器电路与衬底是一体的，并且可以在其正面或背面上形成。 通过使用取向相关蚀刻法在半导体衬底中形成护城河，确定电极间距的护城河的深度来提供用于液晶显示器的电极的非常精确的间隔。

公开(公告)号：US3740276A

公开(公告)日：1973-06-19

申请号：US3740276D

申请日：1970-08-24

申请人： TEXAS INSTRUMENTS INC

发明人： BLAN K

IPC分类号： H01L21/20 ,  H01L21/3065 ,  H01L21/761 ,  H01L21/8222 ,  H01L7/36

CPC分类号： H01L21/3065 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/761 ,  H01L21/8222 ,  Y10S148/05 ,  Y10S148/051 ,  Y10S148/085

摘要： VARIOUS COMPONENTS OF THE NETWORK ENABLING HIGH SWITCHING SPEEDS.

A PROCESS IS DISCLOSED FOR FABRICATING A MULTI-COMPONENT NETWORK UTILIZING A BODY OF HIGH RESISTIVITY SEMICONDUCTOR MATERIAL. THE PROCESS INCLUDES SELECTIVELY ETCHING THE SEMICONDUCTOR SUBSTRATE AND REFORMING IT BY EPITEXIAL DEPOSITION OF SEMICONDUCTOR MATERIAL HAVING DIFFERENT IMPURITY CONCETRATION OR CONDUCTIVITY TYPE. THE PROCESS PROVIDES IMPROVED ISOLATION JUNCTIONS BETWEEN THE

公开(公告)号：US3735210A

公开(公告)日：1973-05-22

申请号：US3735210D

申请日：1971-06-07

申请人： RCA CORP

发明人： KALISH I ,  KHAJEZADEH H

IPC分类号： H01L27/00 ,  H01L29/866 ,  H01L9/00

CPC分类号： H01L29/866 ,  H01L27/00 ,  Y10S148/037 ,  Y10S148/038 ,  Y10S148/049 ,  Y10S148/085 ,  Y10S148/145

摘要： An improved zener diode for monolithic integrated circuits includes a first diffused region of one type conductivity having two portions, one of which portions has a significantly higher maximum impurity concentration than the other portion. A second diffused region of opposite type high conductivity is disposed within both portions of the first region and is separated from each by a PN junction, the PN junction between the second region and the lower conductivity portion being at a significantly greater depth than the PN junction between the second region and the high impurity concentration portion. The electrical contact to the second region is made only over the lower impurity concentration portion where the PN junction is at a significantly greater depth.

摘要翻译： 用于单片集成电路的改进的齐纳二极管包括具有两个部分的一种导电型的第一扩散区域，其中一个部分具有比其他部分显着更高的最大杂质浓度。 相反类型的高导电性的第二扩散区域设置在第一区域的两个部分内，并且由每个PN结分开，第二区域和下部导电部分之间的PN结比PN结明显更大的深度 在第二区域和高杂质浓度部分之间。 与第二区域的电接触只在PN结处于较大深度的较低杂质浓度部分上进行。