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    Maintenance Operations in a DRAM
    811.
    发明申请
    Maintenance Operations in a DRAM 有权
    DRAM中的维护操作

    公开(公告)号：US20170052722A1

    公开(公告)日：2017-02-23

    申请号：US15253736

    申请日：2016-08-31

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton

    IPC: G06F3/06 ,  G11C11/406

    CPC classification number: G06F3/0619 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/1636 ,  G06F13/1689 ,  G06Q10/00 ,  G06Q20/00 ,  G11C7/02 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40618 ,  G11C2211/4061

    Abstract: A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

    Abstract translation: 一种系统包括存储器控制器和具有命令接口和多个存储器组的存储器件，每个存储体具有多行存储器单元。 存储器控制器向存储器件发送自动刷新命令。 响应于自动刷新命令，在第一时间间隔期间，存储器件执行刷新操作以刷新存储器单元，并且存储器件的命令接口在第一时间间隔的持续时间内被置于校准模式。 同时，在第一时间间隔的至少一部分期间，存储器控制器执行存储器件的命令接口的校准。 自动刷新命令可以指定要刷新存储器件的存储体的顺序，使得存储器件以指定的存储体顺序顺序地刷新多个存储体中的相应行。

    Error correction in a memory device
    812.
    发明授权
    Error correction in a memory device 有权
    存储器件中的错误校正

    公开(公告)号：US09575835B2

    公开(公告)日：2017-02-21

    申请号：US14692092

    申请日：2015-04-21

    Applicant: Rambus Inc.

    Inventor： Thomas Vogelsang ,  Suresh N. Rajan ,  Ian P. Shaeffer ,  Frederick A. Ware ,  Wayne F. Ellis

    IPC: G06F11/10 ,  G11C29/44

    CPC classification number: G06F11/1076 ,  G06F11/1048 ,  G06F11/108 ,  G11C11/40 ,  G11C29/24 ,  G11C29/42 ,  G11C29/44 ,  G11C29/50016

    Abstract: A dynamic random access memory (DRAM) array is configured for selective repair and error correction of a subset of the array. Error-correcting code (ECC) is provided to a selected subset of the array to protect a row or partial row of memory cells where one or more weak memory cells are detected. By adding a sense amplifier stripe to the edge of the memory array, the adjacent edge segment of the array is employed to store ECC information associated with the protected subsets of the array. Bit replacement is also applied to defective memory cells. By implementing ECC selectively rather than to the entire array, integrity of the memory array is maintained at minimal cost to the array in terms of area and energy consumption.

    Abstract translation: 动态随机存取存储器（DRAM）阵列被配置用于阵列的子集的选择性修复和纠错。 将纠错码（ECC）提供给阵列的选定子集，以保护检测到一个或多个弱存储器单元的行或部分行的存储单元。 通过向存储器阵列的边缘添加感测放大器条纹，阵列的相邻边缘段用于存储与阵列的受保护子集相关联的ECC信息。 位更换也适用于有缺陷的存储单元。 通过有选择地执行ECC而不是整个阵列，在面积和能量消耗方面，以阵列的最低成本保持存储器阵列的完整性。

    Reduced refresh power
    816.
    发明授权
    Reduced refresh power 有权
    降低刷新功率

    公开(公告)号：US09490002B2

    公开(公告)日：2016-11-08

    申请号：US14801558

    申请日：2015-07-16

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Brent S. Haukness ,  Scott C. Best ,  Gary B. Bronner

    IPC: G11C7/00 ,  G11C11/406

    CPC classification number: G11C11/40611 ,  G11C2211/4061

    Abstract: N out of every M number of refresh commands are ignored (filtered out) by a buffer chip on a memory module. N and M are programmable. The buffer receives refresh commands (e.g., auto-refresh commands) from the command-address channel, but does not issue a proportion of these commands to the DRAMs on the module. This reduces the power consumed by refresh operations. The buffer may replace some auto-refresh (REF) commands with activate (ACT) and precharge (PRE) commands directed to specific rows. These rows may have known ‘weak’ cells that require refreshing more often than a majority of the other rows on the module (or component). By ignoring some auto-refresh commands, and directing some others to specific rows that have ‘weak’ cells, the power consumed by refresh operations can be reduced.

    Abstract translation: 每个M个刷新命令中的N个被存储器模块上的缓冲器芯片忽略（滤除掉）。 N和M是可编程的。 缓冲器从命令地址信道接收刷新命令（例如，自动刷新命令），但不向模块上的DRAM发出这些命令的一部分。 这减少了刷新操作所消耗的功耗。 缓冲区可以用针对特定行的激活（ACT）和预充电（PRE）命令替换一些自动刷新（REF）命令。 这些行可能具有比模块（或组件）上的大多数其他行更频繁刷新的已知“弱”单元格。 通过忽略一些自动刷新命令，并将一些其他命令指向具有“弱”单元格的特定行，可以减少刷新操作消耗的功率。

    Methods and circuits for securing proprietary memory transactions
    817.
    发明授权
    Methods and circuits for securing proprietary memory transactions 有权
    用于保护专有内存事务的方法和电路

    公开(公告)号：US09465961B2

    公开(公告)日：2016-10-11

    申请号：US14098628

    申请日：2013-12-06

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Brian S. Leibowitz ,  Pradeep Batra ,  Trung Am Diep

    IPC: G06F12/14 ,  G06F21/85 ,  G06F21/78 ,  G09C1/00 ,  H04L9/06 ,  H04L9/12

    CPC classification number: G06F21/85 ,  G06F21/78 ,  G06F2221/2107 ,  G09C1/00 ,  H04L9/065 ,  H04L9/12 ,  H04L2209/12 ,  H04L2209/56

    Abstract: Described are systems and method for protecting data and instructions shared over a memory bus and stored in memory. Independent and separately timed stream ciphers for write and read channels allow timing variations between write and read transactions. Data and instructions can be separately encrypted prior to channel encryption to further secure the information. pad generators and related cryptographic circuits are shared for read and write data, and to secure addresses. The cryptographic circuits can support variable data widths, and in some embodiments memory devices incorporate security circuitry that can implement a shared-key algorithm using repurposed memory circuitry.

    Abstract translation: 描述了用于保护在存储器总线上共享并存储在存储器中的数据和指令的系统和方法。 用于写入和读取通道的独立且单独定时的流密码允许写入和读取事务之间的时序变化。 数据和指令可以在通道加密之前单独加密，以进一步保护信息。 垫片发生器和相关的加密电路被共享用于读取和写入数据，并且保护地址。 加密电路可以支持可变数据宽度，并且在一些实施例中，存储器设备包括可以使用重用存储器电路来实现共享密钥算法的安全电路。

    Memory repair method and apparatus based on error code tracking
    818.
    发明授权
    Memory repair method and apparatus based on error code tracking 有权
    基于错误代码跟踪的内存修复方法和设备

    公开(公告)号：US09430324B2

    公开(公告)日：2016-08-30

    申请号：US14285481

    申请日：2014-05-22

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely Tsern

    IPC: G11C29/00 ,  G06F11/10 ,  G06F11/16 ,  G11C29/42 ,  G11C29/44 ,  G06F11/20

    CPC classification number: G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1666 ,  G06F11/20 ,  G11C7/10 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/52 ,  G11C29/70 ,  G11C29/765 ,  G11C2029/4402 ,  H03M13/1575

    Abstract: A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.

    Abstract translation: 公开了一种存储器模块，其包括衬底，输出读取数据的存储器件和缓冲器。 缓冲器具有用于将读取的数据传送到存储器控制器的主界面和耦合到存储器设备的辅助接口以接收读取的数据。 缓冲器包括用于识别所接收的读取数据中的错误并识别与该错误相关联的存储器件中的存储单元位置的错误逻辑。 修复逻辑将替换存储元素映射为与错误相关联的存储单元位置的替代存储元素。

    MEMORY CONTROLLER WITH CLOCK-TO-STROBE SKEW COMPENSATION
    820.
    发明申请
    MEMORY CONTROLLER WITH CLOCK-TO-STROBE SKEW COMPENSATION 有权
    内存控制器，具有时钟对条纹补偿

    公开(公告)号：US20160148671A1

    公开(公告)日：2016-05-26

    申请号：US14951190

    申请日：2015-11-24

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware

    IPC: G11C11/4076 ,  G11C11/409

    CPC classification number: G11C11/4076 ,  G06F1/10 ,  G06F13/1689 ,  G06F13/4243 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18 ,  G11C11/409 ,  G11C2207/2254

    Abstract: A clock signal is transmitted to first and second integrated circuit (IC) components via a clock signal line, the clock signal having a first arrival time at the first IC component and a second, later arrival time at the second IC component. A write command is transmitted to the first and second IC components to be sampled by those components at respective times corresponding to transitions of the clock signal, and write data is transmitted to the first and second IC components in association with the write command. First and second strobe signals are transmitted to the first and second IC components, respectively, to time reception of the first and second write data in those components. The first and second strobe signals are selected from a plurality of phase-offset timing signals to compensate for respective timing skews between the clock signal and the first and second strobe signals.

    Abstract translation: 时钟信号通过时钟信号线发送到第一和第二集成电路（IC）组件，该时钟信号在第一IC组件处具有第一到达时间，而在第二IC组件处具有第二较晚的到达时间。 在对应于时钟信号的转变的各个时刻，写入命令被发送到要被这些分量采样的第一和第二IC组件，并且与写命令相关联地将写数据发送到第一和第二IC组件。 第一和第二选通信号分别被发送到第一和第二IC组件，以便在这些组件中对第一和第二写入数据进行时间接收。 从多个相位偏移定时信号中选择第一和第二选通信号，以补偿时钟信号与第一和第二选通信号之间的各自的定时偏差。

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