公开(公告)号：US20150179248A1

公开(公告)日：2015-06-25

申请号：US14405910

申请日：2013-06-10

Applicant: RAMBUS INC.

Inventor： Dinesh Patil ,  Amir Amirkhany ,  Farrukh Aquil ,  Kambiz Kaviani ,  Frederick A. Ware

IPC: G11C11/4076

CPC classification number: G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F5/065 ,  G06F2205/067 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2272 ,  H03L7/0816

Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

Abstract translation: 实施例通常涉及存储器件。 在一个实施例中，存储器件包括时钟接收器电路，其接收外部时钟信号并提供内部时钟信号。 存储装置还包括具有输入的延迟锁定环路电路（DLL）和接收内部时钟信号的电路。 该电路选择内部时钟信号的哪些脉冲被施加到DLL的输入端，使得从外部时钟信号的至少三个连续脉冲中选出的不超过两个时钟脉冲在预定的时间内被施加到DLL的输入 间隔。 在另一个实施例中，一种方法包括在时钟接收器电路处接收外部时钟信号，从时钟接收器电路接收内部时钟信号，以及选择内部时钟信号的哪些脉冲被施加到DLL的输入，其中不再有 从外部时钟信号的至少三个连续脉冲中选择的两个时钟脉冲在预定间隔期间被施加到DLL的输入端。

公开(公告)号：US20150138895A1

公开(公告)日：2015-05-21

申请号：US14578078

申请日：2014-12-19

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Scott C. Best

IPC: G11C11/4093 ,  G11C11/408

CPC classification number: G11C11/4082 ,  G06F12/06 ,  G06F13/1673 ,  G06F13/1684 ,  G11C5/04 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

Abstract translation: 本文描述的实施例描述了在不同操作模式下使用存储器模块的技术，例如在标准多点模式或动态点对点（DPP）模式（此处也称为增强模式）中， 。 内存模块也可以以不同的配置插入存储系统的插座。

公开(公告)号：US20150106561A1

公开(公告)日：2015-04-16

申请号：US14504767

申请日：2014-10-02

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern

IPC: G06F13/16 ,  G11C7/10

CPC classification number: G11C7/1066 ,  G11C7/10 ,  G11C7/1072

Abstract: A memory component includes a memory bank comprising a plurality of storage cells and a data interface block configured to transfer data between the memory component and a component external to the memory component. The memory component further includes a plurality of column interface buses coupled between the memory bank and the data interface block, wherein a first column interface bus of the plurality of column interface buses is configured to transfer data between a first storage cell of the plurality of storage cells and the data interface block during a first access operation and wherein a second column interface bus of the plurality of column interface buses is configured to transfer the data between the first storage cell and the data interface block during a second access operation.

Abstract translation: 存储器组件包括存储器组，其包括多个存储单元和数据接口块，数据接口块被配置为在存储器组件和存储器组件外部的组件之间传送数据。 存储器组件还包括耦合在存储体和数据接口块之间的多个列接口总线，其中多个列接口总线的第一列接口总线被配置为在多个存储器中的第一存储单元之间传送数据 小区和数据接口块，并且其中多个列接口总线中的第二列接口总线被配置为在第二访问操作期间在第一存储单元和数据接口块之间传送数据。

公开(公告)号：US20150103479A1

公开(公告)日：2015-04-16

申请号：US14515380

申请日：2014-10-15

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan

IPC: G11C11/4093 ,  G06F15/78 ,  G11C11/408 ,  H05K1/18

CPC classification number: H05K1/11 ,  G06F1/184 ,  G06F13/1694 ,  G06F13/4068 ,  G06F15/7803 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C11/4082 ,  G11C11/4093 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10189

Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.

Abstract translation: 这里描述的实施例描述了用于存储器系统的技术。 存储器系统的一个实施方式包括具有多个模块插槽的母板衬底，其中至少一个衬垫具有存储器模块。 第一组数据线设置在母板基板上并耦合到模块插槽。 第一组数据线包括耦合在存储器控制器和第一插座之间的点对点数据线的第一子集，以及耦合在存储器控制器和第二插座之间的点到点数据线的第二子集。 第二组数据线被布置在母板基板上并且耦合在第一插座和第二插座之间。 第一组数据线和第二组数据线可以组成一个存储器通道。

公开(公告)号：US09007853B2

公开(公告)日：2015-04-14

申请号：US14047118

申请日：2013-10-07

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C7/00 ,  G11C11/406 ,  G06F13/16 ,  G11C29/02 ,  G11C29/50 ,  G11C7/22 ,  G11C7/10

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/40615 ,  G11C11/409 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

Abstract: A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write data strobe to compensate for timing drift at the memory device. The memory controller uses read signals as a measure of the drift.

Abstract translation: 存储器系统包括将数据写入存储器件并从存储器件读取数据的存储器控​​制器。 伴随写入数据的写入数据选通信号在写入数据有效时向存储器件指示，而伴随来自存储器件的数据的读取选通器在读取数据有效时向存储器控制器指示。 存储器控制器自适应地控制写入数据选通的相位以补偿存储器件的定时漂移。 存储器控制器使用读取信号作为漂移的度量。

公开(公告)号：US20150043290A1

公开(公告)日：2015-02-12

申请号：US14523922

申请日：2014-10-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Richard E. Perego ,  Craig E. Hampel

IPC: G11C7/22 ,  G11C11/409

CPC classification number: G11C11/4076 ,  G06F1/06 ,  G06F1/105 ,  G06F1/12 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0673 ,  G06F13/1684 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4086 ,  G11C5/063 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50008 ,  G11C29/50012

Abstract: A memory module having integrated circuit (IC) components, a termination structure, an address/control signal path, a clock signal path, multiple data signal paths and multiple strobe signal paths. The strobe signal paths and data signal paths are coupled to respective IC components, and the address/control signal path and clock signal path are coupled in common to all the IC components. The address/control signal path extends along the IC components to the termination structure such that control signals propagating toward the termination structure arrive at address/control inputs of respective IC components at progressively later times corresponding to relative positions of the IC components.

Abstract translation: 具有集成电路（IC）组件，终端结构，地址/控制信号路径，时钟信号路径，多个数据信号路径和多个选通信号路径的存储模块。 选通信号路径和数据信号路径耦合到相应的IC组件，并且地址/控制信号路径和时钟信号路径共同耦合到所有IC组件。 地址/控制信号路径沿着IC组件延伸到终端结构，使得朝向终端结构传播的控制信号在对应于IC组件的相对位置的逐渐更新的时间到达各个IC组件的地址/控制输入。

公开(公告)号：US20140376324A1

公开(公告)日：2014-12-25

申请号：US14241407

申请日：2012-08-31

Applicant: RAMBUS INC.

Inventor： Thomas Vogelsang ,  William N. Ng ,  Frederick A. Ware

IPC: G11C29/04 ,  G11C8/10 ,  G01R31/28

CPC classification number: G11C29/04 ,  G01R31/2851 ,  G11C8/10 ,  G11C29/025 ,  H01L22/34 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/10253 ,  H01L2924/1434 ,  H01L2924/00

Abstract: Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TS V to at least one of a test input and a test evaluation circuit.

Abstract translation: 实施例通常涉及具有硅通孔（TSV）的集成电路器件。 在一个实施例中，集成电路（IC）装置包括TSV的场和地址解码器，其将至少一个TSV可选地耦合到测试输入和测试评估电路中的至少一个。 在另一实施例中，一种方法包括从至少一个IC器件中的TSV领域中选择一个或多个TSV，以及将每个选择的TS V耦合到测试输入和测试评估电路中的至少一个。

公开(公告)号：US20140351629A1

公开(公告)日：2014-11-27

申请号：US14285481

申请日：2014-05-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern

IPC: G06F11/20

CPC classification number: G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1666 ,  G06F11/20 ,  G11C7/10 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/52 ,  G11C29/70 ,  G11C29/765 ,  G11C2029/4402 ,  H03M13/1575

Abstract: A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.

Abstract translation: 公开了一种存储器模块，其包括衬底，输出读取数据的存储器件和缓冲器。 缓冲器具有用于将读取的数据传送到存储器控制器的主界面和耦合到存储器设备的辅助接口以接收读取的数据。 缓冲器包括用于识别所接收的读取数据中的错误并识别与该错误相关联的存储器件中的存储单元位置的错误逻辑。 修复逻辑将替换存储元素映射为与错误相关联的存储单元位置的替代存储元素。

公开(公告)号：US08880818B2

公开(公告)日：2014-11-04

申请号：US14167635

申请日：2014-01-29

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Venu Madhav Kuchibholta

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/16

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0673 ,  G06F13/1694

Abstract: Embodiments of a memory controller are described. This memory controller includes signal connectors, which are electrically coupled to a communication path that includes multiple links, and an interface circuit, which is electrically coupled to the signal connectors. In a first operating mode, the interface circuit communicates with a first memory device via the communication path using spatial multiplexing, in which there are dedicated command/address links and dedicated data links in the communication path. Moreover, in a second operating mode, the interface circuit communicates with a second memory device via the communication path using time multiplexing, in which at least some of the links in the communication path time interleave command/address information and data.

公开(公告)号：US20140293710A1

公开(公告)日：2014-10-02

申请号：US14351955

申请日：2012-10-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  Brian Leibowitz ,  Jared Zerbe

IPC: H03K5/13 ,  G11C7/22

CPC classification number: H03K5/13 ,  G06F13/00 ,  G06F13/1689 ,  G06F13/4243 ,  G11C7/04 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/22 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028

Abstract: An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

Abstract translation: 集成电路包括延迟电路和第一和第二接口电路。 延迟电路将第一定时信号延迟内部延迟以产生内部定时信号。 第一接口电路响应于内部定时信号将数据传送到外部设备。 第二接口电路发送用于捕获外部设备中的数据的外部定时信号。 外部延迟被添加到外部设备中的外部定时信号以产生延迟的外部定时信号。 延迟电路基于延迟的外部定时信号和由第一接口电路发送的校准信号之间的比较来设置内部延迟。