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公开(公告)号：US20230297530A1
公开(公告)日：2023-09-21
申请号：US18163585
申请日：2023-02-02
发明人： Motoshige IKEDA , Yuuji INAE
IPC分类号： G06F13/32 , G06F13/362
CPC分类号： G06F13/32 , G06F13/3625
摘要： A data transfer device that divides and transfers the transfer target data in a burst manner from a transmission-side device to a reception-side device includes a storage device and a control device that controls the storage device to store one piece of the input transfer target data, controls the storage device so that data transfer is performed at a set burst length as a data length of divided data when the one piece of the data is divided by a division number until a last part of the data is sensed, and when the last part of the data is sensed, controls the storage device to adjust the burst length so that a data length of the data coincides with a total of data lengths of data to be transferred, and to transfer the data at the adjusted burst length.
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公开(公告)号：US20230297528A1
公开(公告)日：2023-09-21
申请号：US18152582
申请日：2023-01-10
CPC分类号： G06F13/28 , G06F13/1689 , G06F7/5443
摘要： A semiconductor device capable of preventing a sharp variation in current consumption in neural network processing is provided. A dummy circuit outputs dummy data to at least one or more of n number of MAC circuits and causes the at least one or more of n number of MAC circuits to perform a dummy calculation and to output dummy output data. An output-side DMA controller transfers pieces of normal output data from the n number of MAC circuits to a memory, by use of n number of channels, respectively, and does not transfer the dummy output data to the memory. In this semiconductor device, the at least one or more of n number of MAC circuits perform the dummy calculation in a period from a timing at which the output-side DMA controller ends data transfer to the memory to a timing at which the input-side DMA controller starts data transfer from the memory.
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83.发明授权公开(公告)号：US11762034B2
公开(公告)日：2023-09-19
申请号：US17559091
申请日：2021-12-22
IPC分类号： G01R31/40
CPC分类号： G01R31/40
摘要： The abnormal power supply voltage detection device has a function of accurately detecting the abnormal voltage in accordance with the characteristics of the semiconductor element for each semiconductor chip. Circuit group for operating the adjustment function has a function of preventing the influence of the power supply voltage of the logic system such as control in the semiconductor product malfunctions becomes abnormal. Furthermore, it has a function of detecting the abnormal voltage of the various power supplies in the semiconductor product. It also has a function to test the abnormal voltage detection function in the normal power supply voltage range during use of semiconductor products.
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公开(公告)号：US11742413B2
公开(公告)日：2023-08-29
申请号：US17190891
申请日：2021-03-03
发明人： Atsushi Yoshitomi
CPC分类号： H01L29/66795 , H01L29/66833 , H10B43/35
摘要： Reliability and performance of a semiconductor device are improved. First, a first mask pattern is formed on the semiconductor substrate in each of first to third regions. Next, a second mask pattern made of a material that is different from a material configuring the first mask pattern is formed on a side surface of the first mask pattern and on the semiconductor substrate in each of the first to third regions. Next, by an anisotropic etching process performed to the semiconductor substrate, a plurality of fins protruding from the recessed upper surface of the semiconductor substrate are formed. In the manner, fins each having a different structure from that of a fin in the first region can be formed in the second and third regions.
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公开(公告)号：US11742356B2
公开(公告)日：2023-08-29
申请号：US17687141
申请日：2022-03-04
发明人： Kazuya Uejima , Kazuhiro Koudate
IPC分类号： H01L27/12 , H03K3/356 , H03K19/00 , H03K3/012 , H03K19/0185
CPC分类号： H01L27/1207 , H03K3/012 , H03K3/35613 , H03K19/0013 , H03K19/018528
摘要： Reduction in power consumption of a semiconductor device is achieved. The semiconductor device includes: a first circuit operating at a first power supply voltage and a second circuit operating at a second power supply voltage and including a level shift unit and a switch unit, the first circuit is configured of a low-breakdown-voltage n-type transistor that is an SOTB transistor, and the switch unit is configured of an n-type transistor that is an SOTB transistor. A second power supply voltage is higher than a first power supply voltage, and an impurity concentration of a channel formation region of the n-type transistor is higher than an impurity concentration of a channel formation region of the low-breakdown-voltage n-type transistor.
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公开(公告)号：US11726864B2
公开(公告)日：2023-08-15
申请号：US16821915
申请日：2020-03-17
CPC分类号： G06F11/1004 , G06F9/30189 , G06F11/0772 , G06F11/108 , G06F11/3037
摘要： In a data processing device comprising a memory controller controlling writing/reading of data to/from the memory, a processor requesting writing/reading of data, and an error detection module requesting writing/reading of data to/from the memory controller in accordance with a request from the processor, an error detection module calculates a first error detection code of the first data having a write request from the processor, reads the second data having a read request from the processor from the memory, calculates a second error detection code from the read data, compares the first error detection code and the second error detection code, and transmits the result of the comparison to the external module.
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公开(公告)号：US20230254114A1
公开(公告)日：2023-08-10
申请号：US18059139
申请日：2022-11-28
发明人： Takahiko SUGAHARA
CPC分类号： H04L9/0618 , G06F21/72
摘要： A semiconductor device and a control method thereof capable of satisfying both security requirements and functional safety requirements while suppressing an increase in the circuit scale. The semiconductor device includes: a first encryptor having a first encryption processing unit that performs encryption process on plaintext data input from the outside to generate the first encryption data; a first decryptor having a first decryption processing unit that performs decryption processing in synchronization with an encryption process in the first encryption device to generate the first decryption data for the first encryption data generated in the first encryptor; a comparator that compares the plaintext data with the first decrypted data corresponding to the plaintext data; and a control unit that performs failure determination for the first encryptor and the first decryptor based on the comparison result by the comparator.
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公开(公告)号：US20230253456A1
公开(公告)日：2023-08-10
申请号：US18135426
申请日：2023-04-17
IPC分类号： H01L29/10 , H01L29/786 , H01L29/66 , H01L27/12 , H01L29/417 , H01L29/423 , H01L29/78 , H01L21/768 , H01L29/08 , H01L21/8238 , H01L21/84 , H01L21/265 , H01L29/06 , H01L21/74 , H01L21/8234
CPC分类号： H01L29/1083 , H01L21/74 , H01L21/84 , H01L21/265 , H01L21/76897 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L27/1203 , H01L29/0649 , H01L29/665 , H01L29/0847 , H01L29/0878 , H01L29/4238 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/6681 , H01L29/7824 , H01L29/7833 , H01L29/41783 , H01L29/66477 , H01L29/66537 , H01L29/66545 , H01L29/66553 , H01L29/66628 , H01L29/66742 , H01L29/66757 , H01L29/66772 , H01L29/78606 , H01L29/78621 , H01L29/78651 , H01L29/78654
摘要： Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
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公开(公告)号：US20230251418A1
公开(公告)日：2023-08-10
申请号：US17666948
申请日：2022-02-08
CPC分类号： G02B6/12004 , G02B6/125 , G02B6/136 , G02B6/132 , G02B2006/12061 , G02B2006/12142
摘要： A semiconductor device includes: a semiconductor substrate; an insulating layer formed on the semiconductor substrate; an optical waveguide formed on the insulating layer, extending in a first direction in a plan view, and being made of silicon; and an interlayer insulating film formed on the insulating layer to cover the optical waveguide. In this case, a crystal surface of a side surface of the optical waveguide is a (111) surface.
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公开(公告)号：US11714107B2
公开(公告)日：2023-08-01
申请号：US17666918
申请日：2022-02-08
发明人： Noriaki Matsuno , Shingo Sakamoto
IPC分类号： G01R15/06
CPC分类号： G01R15/06
摘要： A voltage divider circuit includes: a first voltage divider having first and second capacitors, and an output node configured to output a divider voltage from between the first and second capacitors; a second voltage divider having third and fourth capacitors, and first to third switches, and being connected in parallel to the first voltage divider; and a fourth switch provided between the output node and a connection node of the third and fourth capacitors. In the voltage divider circuit, the switches are controlled based on controlling periods.
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