公开(公告)号：US08144972B2

公开(公告)日：2012-03-27

申请号：US12232460

申请日：2008-09-17

Applicant: Chung Woo Cho ,  Seon Ha Kang ,  Young Hwan Shin ,  Jong Jin Lee

Inventor： Chung Woo Cho ,  Seon Ha Kang ,  Young Hwan Shin ,  Jong Jin Lee

IPC: G06K9/00

CPC classification number: H05K3/0008 ,  H05K1/0269 ,  H05K3/0005 ,  H05K3/0082 ,  H05K3/108 ,  H05K3/421 ,  H05K3/426 ,  H05K3/429 ,  H05K2201/09563 ,  H05K2201/09918 ,  H05K2203/1394

Abstract: The present invention relates to a method for manufacturing a printed circuit board and an apparatus for manufacturing the same; and, more particularly, to a method for manufacturing a printed circuit board and an apparatus for manufacturing the same capable of improving the degree of matching between contact holes and pads by correcting exposure position data of an exposing process for forming the pads according to positions of the contact holes.

Abstract translation: 本发明涉及印刷电路板的制造方法及其制造装置。 更具体地说，涉及一种用于制造印刷电路板的方法及其制造方法，其能够通过根据位置来校正用于形成焊盘的曝光处理的曝光位置数据，从而提高接触孔和焊盘之间的匹配度 接触孔。

公开(公告)号：US07952951B2

公开(公告)日：2011-05-31

申请号：US12483440

申请日：2009-06-12

Applicant: Jong Jin Lee

Inventor： Jong Jin Lee

IPC: G11C17/16

CPC classification number: H01H85/0241 ,  G11C17/16 ,  G11C29/787 ,  H01H2085/0275 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed are a fuse box and a semiconductor integrated circuit having the same. The semiconductor integrated circuit includes a plurality of banks, column control blocks, and column fuse blocks. The plurality of banks including a plurality of mat rows and mat columns. The banks are arranged in row and column directions and disposed away from each other. The column control blocks are disposed in a space between the banks which are extended to the column direction. The column fuse blocks are disposed adjacent to the column control blocks and have a plurality of fuse boxes. The fuse boxes include fuse sets arranged in two rows. The fuse boxes are disposed to correspond to the one mat column. Each fuse box has an interconnection fuse and address fuses which are arranged with a constant interval and are the same type.

Abstract translation: 公开了一种保险丝盒和具有该保险丝盒的半导体集成电路。 半导体集成电路包括多个组，列控制块和列熔丝块。 多个存储体包括多个垫子行和垫子列。 银行按行和列方向排列，彼此远离。 列控制块设置在延伸到列方向的堤之间的空间中。 列保险丝块被布置成与列控制块相邻并且具有多个保险丝盒。 保险丝盒包括两列排列的保险丝套件。 保险丝盒被设置成对应于一个垫柱。 每个保险丝盒具有互连熔断器和地址保险丝，它们以恒定间隔布置并且是相同类型的。

公开(公告)号：US07833890B2

公开(公告)日：2010-11-16

申请号：US12457366

申请日：2009-06-09

Applicant: Won-joo Kim ,  June-mo Koo ,  Seung-hwan Song ,  Suk-pil Kim ,  Yoon-dong Park ,  Jong-jin Lee

Inventor： Won-joo Kim ,  June-mo Koo ,  Seung-hwan Song ,  Suk-pil Kim ,  Yoon-dong Park ,  Jong-jin Lee

IPC: H01L21/4763

CPC classification number: H01L21/28273 ,  H01L21/28282 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/792

Abstract: Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.

Abstract translation: 示例性实施例涉及半导体器件及其制造方法。 根据示例实施例的半导体器件可以在读取操作期间具有减小的干扰，并且减少短信道效应。 半导体器件可以包括具有主体和从主体突出的一对鳍片的半导体衬底。 可以在一对翅片的内侧壁的上部形成内隔离层绝缘层，以减少对一对翅片之间的区域的入口。 栅极电极可以覆盖一对鳍片的外部侧壁的一部分，并且可以跨越内部间隔物绝缘层延伸，以便在一对鳍片之间限定空隙。 栅绝缘层可以插入在栅电极和一对鳍之间。

公开(公告)号：US07807215B2

公开(公告)日：2010-10-05

申请号：US11524401

申请日：2006-09-21

Applicant: Jong Jin Lee ,  Young Hwan Shin ,  Jae Min Choi ,  Chang Yul Oh

Inventor： Jong Jin Lee ,  Young Hwan Shin ,  Jae Min Choi ,  Chang Yul Oh

IPC: B05D5/12 ,  B65B33/00

CPC classification number: B32B38/04 ,  B32B37/12 ,  B32B2038/047 ,  B32B2311/12 ,  B32B2457/08 ,  H05K3/0035 ,  H05K3/0097 ,  H05K3/025 ,  H05K3/421 ,  H05K2203/0152 ,  H05K2203/1388 ,  H05K2203/1536 ,  Y10T156/1052 ,  Y10T156/1082

Abstract: Disclosed herein is a method of manufacturing a copper-clad laminate for Via-On-Pad application. The pad includes the steps of providing a first copper foil layer and a second copper foil layer, on the first surfaces of which protective layers are formed; placing two sets of a first copper foil layer, an insulating layer and a second copper foil layer above and below an adhesive layer, respectively; removing the protective layers, which have been respectively formed on the second copper foil layers, and parts of the second copper foil layers; forming via holes by removing parts of the insulating layers through the regions from which the parts of the second copper foil layers have been removed, using laser processing; and forming two copper-clad laminates by removing the protective layers, which have been respectively formed on one surface of one first copper foil layer and one surface of the other first copper foil layer, and the adhesive layer.

Abstract translation: 本文公开了一种制造用于Via-On-Pad应用的覆铜层压板的方法。 该垫包括在形成有保护层的第一表面上提供第一铜箔层和第二铜箔层的步骤; 在粘合剂层上分别放置两组第一铜箔层，绝缘层和第二铜箔层; 去除分别形成在第二铜箔层上的保护层和第二铜箔层的部分; 通过使用激光加工从已除去了第二铜箔层的部分的区域去除绝缘层的一部分来形成通孔; 并且通过去除分别形成在一个第一铜箔层的一个表面和另一个第一铜箔层的一个表面上的保护层和粘合剂层来形成两个覆铜层压板。

公开(公告)号：US20100233073A1

公开(公告)日：2010-09-16

申请号：US12593046

申请日：2008-08-05

Applicant: Sang Hoon Hyun ,  Hyun Jong Cho ,  Jong Jin Lee

Inventor： Sang Hoon Hyun ,  Hyun Jong Cho ,  Jong Jin Lee

IPC: C01F7/04

CPC classification number: C04B35/6268 ,  C01F7/043 ,  C01P2002/72 ,  C01P2002/76 ,  C04B35/44 ,  C04B35/62675 ,  C04B2235/3203

Abstract: The present invention relates to a method for preparing high-purity alpha-lithium aluminate (α-LiAlO2). More specifically, the invention relates to a method for preparing alpha-lithium aluminate, which comprises mixing Al(OH)3 and Li2CO3 at a molar ratio of from 1:1 to 3:1 and heat-treating the mixture at a temperature of 500-800° C. and which can prepare high-purity alpha-lithium aluminate without needing to carry out a washing process.

Abstract translation: 本发明涉及一种制备高纯度α-铝酸锂（α-LiAlO 2）的方法。 更具体地说，本发明涉及一种制备铝酸锂的方法，其包括以1:1至3:1的摩尔比混合Al（OH）3和Li 2 CO 3，并在500℃的温度下对混合物进行热处理 -800℃，可以制备高纯度的铝酸锂，不需要进行洗涤。

公开(公告)号：US20100147575A1

公开(公告)日：2010-06-17

申请号：US12614057

申请日：2009-11-06

Applicant: Han-Ul Lee ,  Young-Hwan Shin ,  Jong-Jin Lee

Inventor： Han-Ul Lee ,  Young-Hwan Shin ,  Jong-Jin Lee

IPC: H05K1/11 ,  C25D5/02

CPC classification number: H05K1/119 ,  H05K3/0038 ,  H05K3/427 ,  H05K2201/09563 ,  H05K2201/09827 ,  H05K2203/1572

Abstract: A printed circuit board and a method of manufacturing the printed circuit board are disclosed. The method of manufacturing a printed circuit board can include: processing a first hole, which has a tapered shape, in one side of a substrate by using a laser drill; processing a second hole, which has a tapered shape and which connects with the first hole, in the other side of the substrate by using a laser drill in a position corresponding to that of the first hole; and forming a conductive portion, which electrically connects both sides of the substrate through the first hole and the second hole, by performing plating. This method may be used for providing reliable interlayer connections.

Abstract translation: 公开了印刷电路板和印刷电路板的制造方法。 制造印刷电路板的方法可以包括：通过使用激光钻孔在基板的一侧处理具有锥形形状的第一孔; 通过使用激光钻头处理与第一孔相对应的位置，在基板的另一侧处理具有锥形形状并与第一孔连接的第二孔; 并且通过执行电镀形成导电部分，其通过第一孔和第二孔电连接基板的两侧。 该方法可用于提供可靠的层间连接。

公开(公告)号：US20100059267A1

公开(公告)日：2010-03-11

申请号：US12358543

申请日：2009-01-23

Applicant: Jong-Jin LEE

Inventor： Jong-Jin LEE

IPC: H05K1/05 ,  H05K3/00 ,  H01L23/14

CPC classification number: H05K3/0058 ,  H05K1/0271 ,  H05K3/022 ,  H05K3/382 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/09136 ,  Y10T29/49124

Abstract: A printed circuit board and a method of manufacturing the printed circuit board are disclosed. In an embodiment of the present invention, the method of manufacturing a printed circuit board can include: providing a pair of conductive layers, in which roughness of one surface of one of the pair of conductive layers is different from roughness of one surface of the other of the pair of conductive layers; and stacking the pair of the conductive layers on a dielectric layer such that one surface of one of the pair of conductive layers faces one surface of the dielectric layer and one surface of the other of the pair of conductive layers faces another surface of the dielectric layer.

Abstract translation: 公开了印刷电路板和印刷电路板的制造方法。 在本发明的实施例中，制造印刷电路板的方法可以包括：提供一对导电层，其中一对导电层之一的一个表面的粗糙度与另一个导电层的一个表面的粗糙度不同 的一对导电层; 并且将所述一对导电层堆叠在电介质层上，使得所述一对导电层中的一个导电层的一个表面面对所述电介质层的一个表面，并且所述一对导电层中另一个表面的一个表面面向所述电介质层的另一个表面 。

公开(公告)号：US07671926B2

公开(公告)日：2010-03-02

申请号：US11012330

申请日：2004-12-16

Applicant: Jong Jin Lee ,  Chang Kap Nam ,  Ryo Young Mang

Inventor： Jong Jin Lee ,  Chang Kap Nam ,  Ryo Young Mang

IPC: H04N7/16 ,  H04N5/38

CPC classification number: H04N5/40 ,  H04N5/38 ,  H04N7/06 ,  H04N9/77

Abstract: Disclosed herein is a Radio Frequency (RF) modulator. The RF modulator includes a Chrominance-to-Luminance (C/L) delay compensation unit for receiving a video signal and compensating for a time delay between the chrominance and luminance signals of the video signal, and a modulation unit for receiving the video signal, which is compensated for by the C/L delay compensation unit, and an audio signal and converting the video and audio signal into a preset frequency-band RE signal. The C/L delay compensation unit and the modulation unit are packaged in a single package.

Abstract translation: 本文公开了一种射频（RF）调制器。 RF调制器包括色度亮度（C / L）延迟补偿单元，用于接收视频信号并补偿视频信号的色度和亮度信号之间的时间延迟，以及用于接收视频信号的调制单元， 其被C / L延迟补偿单元补偿，并且音频信号并将视频和音频信号转换成预设的频带RE信号。 C / L延迟补偿单元和调制单元封装在单个封装中。

公开(公告)号：US20100006821A1

公开(公告)日：2010-01-14

申请号：US12444956

申请日：2007-10-08

Applicant: Jung Bum Choi ,  Jong JIn Lee ,  Seung-Jun Shin ,  Rae-Sik Chung

Inventor： Jung Bum Choi ,  Jong JIn Lee ,  Seung-Jun Shin ,  Rae-Sik Chung

IPC: H01L29/66 ,  H01L21/336

CPC classification number: H01L21/32139 ,  B82Y10/00 ,  H01L21/0277 ,  H01L29/127 ,  H01L29/66439 ,  H01L29/7613

Abstract: The present invention relates to a method of fabricating a nanoscale multi-junction quantum dot device wherein it can minimize constraints depending on the number or shape of patterns and a line width, and in particular, overcome shortcomings depending on the proximity effect occurring between patterns while employing the advantages of electron beam lithography to the utmost by forming a new conductive layer between the patterns and utilizing it as a new pattern.

Abstract translation: 本发明涉及一种制造纳米级多结量子点器件的方法，其中它可以根据图案的数量或形状以及线宽来最小化约束，并且特别地，克服了取决于在图案之间发生的邻近效应的缺点，而 通过在图案之间形成新的导电层并将其用作新图案，最大限度地利用电子束光刻的优点。

公开(公告)号：US20090253255A1

公开(公告)日：2009-10-08

申请号：US12457366

申请日：2009-06-09

Applicant: Won-joo Kim ,  June-mo Koo ,  Seung-hwan Song ,  Suk-pil Kim ,  Yoon-dong Park ,  Jong-jin Lee

Inventor： Won-joo Kim ,  June-mo Koo ,  Seung-hwan Song ,  Suk-pil Kim ,  Yoon-dong Park ,  Jong-jin Lee

IPC: H01L21/28

CPC classification number: H01L21/28273 ,  H01L21/28282 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/792

Abstract: Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.

Abstract translation: 示例性实施例涉及半导体器件及其制造方法。 根据示例实施例的半导体器件可以在读取操作期间具有减小的干扰，并且减少短信道效应。 半导体器件可以包括具有主体和从主体突出的一对鳍片的半导体衬底。 可以在一对翅片的内侧壁的上部形成内隔离层绝缘层，以减少对一对翅片之间的区域的入口。 栅极电极可以覆盖一对鳍片的外部侧壁的一部分，并且可以跨越内部间隔物绝缘层延伸，以便在一对鳍片之间限定空隙。 栅绝缘层可以插入在栅电极和一对鳍之间。