公开(公告)号：US06844604B2

公开(公告)日：2005-01-18

申请号：US09776059

申请日：2001-02-02

Applicant: Jongho Lee ,  Nae-In Lee

Inventor： Jongho Lee ,  Nae-In Lee

IPC: H01L21/8247 ,  H01L21/02 ,  H01L21/28 ,  H01L21/31 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L29/51 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/94 ,  H01L29/76

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7881 ,  H01L29/94

Abstract: A multi-layer dielectric layer structure for a semiconductor device. The multi-layer dielectric layer structure comprises a silicate interface layer having a dielectric constant greater than that of silicon nitride and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises one or more ordered pairs of first and second layers. With the present invention, the dielectric constant of the high-k dielectric layer can be optimized while improving interface characteristics. With a higher crystallization temperature realized by forming the multi-layer structure, each of whose layers is not more than the critical thickness, leakage current can be reduced, thereby improving device performance.

Abstract translation: 一种用于半导体器件的多层电介质层结构。 多层介电层结构包括具有大于氮化硅的介电常数的硅酸盐界面层和覆盖硅酸盐界面层的高k电介质层。 高k电介质层包括一个或多个有序的第一和第二层对。 利用本发明，可以优化高k电介质层的介电常数，同时改善界面特性。 通过形成多层结构实现的更高的结晶温度，其层数不大于临界厚度，可以降低漏电流，从而提高器件性能。

公开(公告)号：US06750532B2

公开(公告)日：2004-06-15

申请号：US10336604

申请日：2003-01-03

Applicant: Hwa-Sung Rhee ,  Geum-Jong Bae ,  Tae-Hee Choe ,  Sang-Su Kim ,  Nae-In Lee

Inventor： Hwa-Sung Rhee ,  Geum-Jong Bae ,  Tae-Hee Choe ,  Sang-Su Kim ,  Nae-In Lee

IPC: H01L29167

CPC classification number: H01L21/2807 ,  H01L21/823842

Abstract: In a CMOS semiconductor device having a substrate, a gate insulating layer formed on the substrate, at least one first polysilicon gate formed over the substrate in at least one PMOS transistor region, and at least one second polysilicon gate formed over the substrate in at least one NMOS transistor region, a total amount of Ge in the first polysilicon gate is the same as that in the second polysilicon gate, a distribution of Ge concentration in the first and/or second polysilicon gate is different according to a distance from the gate insulating layer, and Ge concentration in a portion of the first polysilicon gate adjacent to the gate insulating layer is higher than that in the second polysilicon gate. The Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than two times as high as that in the second polysilicon gate. For example, it is preferable that the Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than 20%, and Ge concentration in a portion of the second polysilicon gate adjacent to the gate insulating layer is below 10%.

Abstract translation: 在具有衬底的CMOS半导体器件中，形成在衬底上的栅极绝缘层，至少一个在至少一个PMOS晶体管区域中的衬底上形成的第一多晶硅栅极和至少一个第二多晶硅栅极，至少形成在衬底上至少一个 一个NMOS晶体管区域，第一多晶硅栅极中的Ge的总量与第二多晶硅栅极中的Ge的总量相同，第一和/或第二多晶硅栅极中的Ge浓度的分布根据与栅极绝缘的距离而不同 与栅极绝缘层相邻的第一多晶硅栅极的一部分中的Ge层浓度高于第二多晶硅栅极中的Ge浓度。 与栅极绝缘层相邻的第一多晶硅栅极部分的Ge浓度比第二多晶硅栅极中的Ge浓度高两倍。 例如，与栅极绝缘层相邻的第一多晶硅栅极的Ge浓度优选大于20％，与栅极绝缘层相邻的第二多晶硅栅极的部分中的Ge浓度低于10 ％。

公开(公告)号：US06716689B2

公开(公告)日：2004-04-06

申请号：US10274035

申请日：2002-10-21

Applicant: Geum-Jong Bae ,  Nae-In Lee ,  Hwa-Sung Rhee ,  Sang-Su Kim ,  Jung-Il Lee

Inventor： Geum-Jong Bae ,  Nae-In Lee ,  Hwa-Sung Rhee ,  Sang-Su Kim ,  Jung-Il Lee

IPC: H01L21338

CPC classification number: H01L29/6653 ,  H01L21/28114 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833

Abstract: A MOS transistor having a T-shaped gate electrode and a method for fabricating the same are provided, wherein the MOS transistor includes a T-shaped gate electrode on a semiconductor substrate; an L-shaped lower spacer disposed at both sides of the gate electrode to cover a top surface of the semiconductor substrate; and low-, mid-, and high-concentration impurity regions formed in the semiconductor substrate of both sides of the gate electrode. The high-concentration impurity region is disposed in the semiconductor substrate next to the lower spacer and the mid-concentration impurity region is disposed between the high- and low-concentration impurity regions. A MOS transistor according to the present invention provides a decrease in a capacitance, a decrease in a channel length, and an increase in a cross-sectional area of the gate electrode. At the same time, the mid-concentration impurity region provides a decrease in a source/drain resistance Rsd.

公开(公告)号：US5674782A

公开(公告)日：1997-10-07

申请号：US611432

申请日：1996-03-04

Applicant: Nae-in Lee ,  Moon-han Park ,  Young-wug Kim ,  Kwan-young Oh

Inventor： Nae-in Lee ,  Moon-han Park ,  Young-wug Kim ,  Kwan-young Oh

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/3213

CPC classification number: H01L21/02071 ,  H01L21/28061 ,  H01L21/32135

Abstract: A method for efficiently removing by-products produced in dry-etching a fabricated structure of a semiconductor device, particularly, a polycide structure. The method includes the steps of sequentially forming a polysilicon layer and a refractory metal silicide layer to overlie previously fabricated structures on a semiconductor substrate, dry-etching the polysilicon layer and the refractory metal silicide layer to form a patterned polysilicon layer and a patterned refractory metal silicide layer, and thermal treating the resultant structure to remove at least one kind of by-product produced in the dry-etching step at a temperature higher than the boiling point of any by-product.

Abstract translation: 一种用于有效地除去在干法蚀刻半导体器件，特别是多晶硅化物结构的制造结构中产生的副产物的方法。 该方法包括以下步骤：顺序地形成多晶硅层和难熔金属硅化物层以覆盖半导体衬底上先前制造的结构，干蚀刻多晶硅层和难熔金属硅化物层以形成图案化的多晶硅层和图案化的难熔金属 硅化物层，并对所得结构进行热处理，以在高于任何副产物的沸点的温度下除去在干蚀刻步骤中产生的至少一种副产物。

公开(公告)号：US20180076103A1

公开(公告)日：2018-03-15

申请号：US15629072

申请日：2017-06-21

Applicant: Hyung-jun JEON ,  Nae-in LEE ,  Byung-lyul PARK

Inventor： Hyung-jun JEON ,  Nae-in LEE ,  Byung-lyul PARK

IPC: H01L23/045 ,  H01L23/047 ,  H01L25/10

CPC classification number: H01L23/045 ,  H01L23/047 ,  H01L23/3128 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/3511

Abstract: A semiconductor package of a package on package type includes a lower package including a printed circuit board (PCB) substrate including a plurality of base layers and a cavity penetrating the plurality of base layers, a first semiconductor chip in the cavity. a redistribution structure on a first surface of the PCB substrate and on an active surface of the first semiconductor chip, a first cover layer covering the redistribution structure, and the second cover layer covering a second surface of the PCB substrate and an inactive surface of the first semiconductor chip, and an upper package on the second cover layer of the lower package and including a second semiconductor chip.

公开(公告)号：US20160197188A1

公开(公告)日：2016-07-07

申请号：US15071502

申请日：2016-03-16

Applicant: Dong-Suk Shin ,  Myung-Sun Kim ,  Seong-Jin Nam ,  Pan-Kwi Park ,  Hoi-Sung Chung ,  Nae-In Lee

Inventor： Dong-Suk Shin ,  Myung-Sun Kim ,  Seong-Jin Nam ,  Pan-Kwi Park ,  Hoi-Sung Chung ,  Nae-In Lee

IPC: H01L29/78 ,  H01L29/51 ,  H01L27/11 ,  H01L29/45 ,  H01L27/088 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L27/1104 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/28247 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/1116 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/513 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7827 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

Abstract: In a semiconductor device, a first active region has a first Σ-shape, and the second active region has a second Σ-shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm.

公开(公告)号：US20160163589A1

公开(公告)日：2016-06-09

申请号：US14955988

申请日：2015-12-01

Applicant: Woo-Jin Lee ,  Byung-Hee Kim ,  Sang-Hoon Ahn ,  Woo-Kyung You ,  Jong-Min Baek ,  Nae-In Lee

Inventor： Woo-Jin Lee ,  Byung-Hee Kim ,  Sang-Hoon Ahn ,  Woo-Kyung You ,  Jong-Min Baek ,  Nae-In Lee

IPC: H01L21/768

CPC classification number: H01L21/76807 ,  H01L21/76816 ,  H01L21/76849 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2221/1047

Abstract: A method of forming a semiconductor device can include forming an insulation layer using a material having a composition selected to provide resistance to subsequent etching process. The composition of the material can be changed to reduce the resistance of the material to the subsequent etching process at a predetermined level in the insulation layer. The subsequent etching process can be performed on the insulation layer to remove an upper portion of the insulation layer above the predetermined level and leave a lower portion of the insulation layer below the predetermined level between adjacent conductive patterns extending through the lower portion of the insulation layer. A low-k dielectric material can be formed on the lower portion of the insulation layer between the adjacent conductive patterns to replace the upper portion of the insulation layer above the predetermined level.

Abstract translation: 形成半导体器件的方法可以包括使用具有选择为提供对后续蚀刻工艺的电阻的组成的材料形成绝缘层。 可以改变材料的组成以将材料的电阻降低到绝缘层中预定水平的后续蚀刻工艺。 可以在绝缘层上执行随后的蚀刻工艺，以将绝缘层的上部去除在预定水平以上，并且将绝缘层的下部分留在延伸穿过绝缘层的下部的相邻导电图案之间的预定水平以下 。 可以在相邻导电图案之间的绝缘层的下部上形成低k介电材料，以将绝缘层的上部替换为高于预定水平。

公开(公告)号：US20160079424A1

公开(公告)日：2016-03-17

申请号：US14951932

申请日：2015-11-25

Applicant: Dong-Suk SHIN ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

Inventor： Dong-Suk SHIN ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/167

CPC classification number: H01L29/7848 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

公开(公告)号：US08314465B2

公开(公告)日：2012-11-20

申请号：US13039811

申请日：2011-03-03

Applicant: Jong-Ho Lee ,  Nae-In Lee

Inventor： Jong-Ho Lee ,  Nae-In Lee

IPC: H01L29/76

CPC classification number: H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7881 ,  H01L29/94

Abstract: A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides.

Abstract translation: 半导体器件包括硅酸盐界面层和覆盖硅酸盐界面层的高k电介质层。 高k电介质层包括金属合金氧化物。

公开(公告)号：US20110049587A1

公开(公告)日：2011-03-03

申请号：US12926227

申请日：2010-11-03

Applicant: Chang-wook Moon ,  Hyun-deok Yang ,  Joong S. Jeon ,  Hwa-sung Rhee ,  Nae-in Lee ,  Weiwei Chen

Inventor： Chang-wook Moon ,  Hyun-deok Yang ,  Joong S. Jeon ,  Hwa-sung Rhee ,  Nae-in Lee ,  Weiwei Chen

IPC: H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

Abstract: Example embodiments relate to a method of forming a germanium (Ge) silicide layer, a semiconductor device including the Ge silicide layer, and a method of manufacturing the semiconductor device. A method of forming a Ge silicide layer according to example embodiments may include forming a metal layer including vanadium (V) on a silicon germanium (SiGe) layer. The metal layer may have a multiple-layer structure and may further include at least one of platinum (Pt) and nickel (Ni). The metal layer may be annealed to form the germanium silicide layer. The annealing may be performed using a laser spike annealing (LSA) method.

Abstract translation: 示例性实施例涉及形成锗（锗）硅化物层的方法，包括锗硅化物层的半导体器件以及制造半导体器件的方法。 根据示例性实施方案的形成锗硅化物层的方法可以包括在硅锗（SiGe）层上形成包括钒（V）的金属层。 金属层可以具有多层结构，并且还可以包括铂（Pt）和镍（Ni）中的至少一种。 金属层可以退火以形成硅化锗层。 可以使用激光尖峰退火（LSA）方法进行退火。