公开(公告)号：US20230360694A1

公开(公告)日：2023-11-09

申请号：US18195877

申请日：2023-05-10

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Ming Li

IPC: G11C11/4093 ,  G11C11/4096 ,  G11C5/02 ,  G11C5/04 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H01L23/48 ,  G11C11/406

CPC classification number: G11C11/4093 ,  G11C11/4096 ,  G11C5/025 ,  G11C5/04 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  G11C5/02 ,  H01L23/481 ,  G11C11/406 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L24/73

Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

公开(公告)号：US20230359572A1

公开(公告)日：2023-11-09

申请号：US18135095

申请日：2023-04-14

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

IPC: G11C7/22 ,  G06F1/06 ,  G06F1/04 ,  G06F1/10 ,  G06F1/08 ,  G06F13/16

CPC classification number: G06F13/1689 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G06F13/161 ,  G06F13/1657 ,  G11C7/222 ,  G11C7/04

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

公开(公告)号：US11803489B2

公开(公告)日：2023-10-31

申请号：US17849450

申请日：2022-06-24

Applicant: Rambus Inc.

Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Ullhas Prabhu ,  Makarand Ajit Shirasgaonkar

IPC: G06F13/16

CPC classification number: G06F13/1668 ,  Y02D10/00

Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.

公开(公告)号：US20230342310A1

公开(公告)日：2023-10-26

申请号：US18025571

申请日：2021-08-30

Applicant: Rambus Inc.

Inventor： Steven C. Woo ,  Thomas Vogelsang

IPC: G06F13/16 ,  G06N3/048 ,  G06N3/084

CPC classification number: G06F13/1668 ,  G06N3/048 ,  G06N3/084 ,  G06F2213/16

Abstract: An application-specific integrated circuit for an artificial neural network is integrated with a high-bandwidth memory. A processing die with tiled neural-network processing units is bonded to a stack of memory dies with memory banks laid out to establish relatively short connections to overlying processing units. The memory banks form vertical groups of banks for each overlying processing unit. A switch matrix on the processing die allows each processing unit to communicate with its vertical group of banks via a short, fast inter-die memory channel or with more remote groups of banks under neighboring processing units.

公开(公告)号：US20230333927A1

公开(公告)日：2023-10-19

申请号：US18095341

申请日：2023-01-10

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Craig E. Hampel

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/16 ,  H03M13/09

CPC classification number: G06F11/1004 ,  G06F11/0703 ,  G06F11/073 ,  G06F11/1679 ,  H03M13/09

Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation

公开(公告)号：US20230325309A1

公开(公告)日：2023-10-12

申请号：US18210387

申请日：2023-06-15

Applicant: Rambus Inc.

Inventor： Thomas J. Sheffler ,  Lawrence Lai ,  Liang Peng ,  Bohuslav Rychlik

IPC: G06F12/02 ,  G11C7/22 ,  G11C8/10 ,  G11C7/10

CPC classification number: G06F12/023 ,  G11C7/22 ,  G11C8/10 ,  G11C7/1006 ,  G11C7/1039 ,  H05K999/99 ,  G11C2207/107 ,  G06F2212/2024

Abstract: A memory device having a DRAM core and a register stores first data in the register before receiving first and second memory access commands via a command interface and before receiving second data via a data interface. The memory device responds to the first memory access command by writing the first data from the register to the DRAM core and responds to the second memory access command by writing the second data from the data interface to the DRAM core.

公开(公告)号：US11782788B2

公开(公告)日：2023-10-10

申请号：US17585654

申请日：2022-01-27

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C29/00 ,  G06F12/0882 ,  G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F12/02

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/3037 ,  G06F12/0246 ,  G06F12/0882 ,  G06F2212/7201

Abstract: A hybrid volatile/non-volatile memory employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). The memory supports error-detection and correction (EDC) techniques by allocating a fraction of DRAM storage to information calculated for each unit of stored data that can be used to detect and correct errors. An interface between the DRAM cache and NVM executes a wear-leveling scheme that aggregates and distributes NVM data and EDC write operations in a manner that prolongs service life.

公开(公告)号：US20230305915A1

公开(公告)日：2023-09-28

申请号：US18092556

申请日：2023-01-03

Applicant: Rambus Inc.

Inventor： Thomas J. GIOVANNINI ,  Catherine CHEN ,  Scott C. BEST ,  John Eric LINSTADT ,  Frederick A. WARE

IPC: G06F11/07 ,  G11C29/44 ,  G06F13/00 ,  G11C5/04 ,  G11C7/20 ,  G11C8/12 ,  G11C29/26

CPC classification number: G06F11/079 ,  G06F11/073 ,  G06F11/0772 ,  G06F13/00 ,  G11C5/04 ,  G11C7/20 ,  G11C8/12 ,  G11C29/26 ,  G11C29/44

Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.

公开(公告)号：US20230297151A1

公开(公告)日：2023-09-21

申请号：US18068437

申请日：2022-12-19

Applicant: Rambus Inc.

Inventor： Deborah Lindsey Dressler ,  Julia Kelly Cline ,  Wayne Frederick Ellis

IPC: G06F1/28 ,  G11C5/06 ,  G06F1/3287 ,  G06F1/3234 ,  G06F13/42

CPC classification number: G06F1/28 ,  G06F1/3275 ,  G06F1/3287 ,  G06F13/4273 ,  G11C5/063

Abstract: A multi-element device includes a plurality of memory elements, each of which includes a memory array, access circuitry to control access to the memory array, and power control circuitry. The power control circuitry, which includes one or more control registers for storing first and second control values, controls distribution of power to the access circuitry in accordance with the first control value, and controls distribution of power to the memory array in accordance with the second control value. Each memory element also includes sideband circuitry for enabling a host system to set at least the first control value and the second control value in the one or more control registers.

公开(公告)号：US11762737B2

公开(公告)日：2023-09-19

申请号：US17956516

申请日：2022-09-29

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent S. Haukness ,  Lawrence Lai

IPC: H03M13/27 ,  H04L27/34 ,  H04L1/00 ,  H03M13/25 ,  G06F11/10

CPC classification number: G06F11/1076 ,  G06F11/1048

Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.