公开(公告)号：US20080000876A1

公开(公告)日：2008-01-03

申请号：US11648026

申请日：2006-12-28

申请人： Sang-Soo Park ,  Hyun-Suk Sung ,  Dong-Goo Choi

发明人： Sang-Soo Park ,  Hyun-Suk Sung ,  Dong-Goo Choi

IPC分类号： C23F1/00 ,  H01L21/306 ,  H01L21/302

CPC分类号： H01L21/68735 ,  H01J37/32623 ,  H01J37/32642 ,  H01L21/67069

摘要： A plasma etching apparatus includes a plasma processing chamber, an electro static chuck installed in the plasma processing chamber and providing a region where a wafer is to be placed, and a focus ring surrounding an edge of the wafer at an edge portion of the electro static chuck and including: a first region surrounding the edge of the wafer; and a second region disposed under a bottom surface of the wafer. The first region has a surface disposed higher than that of the wafer.

摘要翻译： 等离子体蚀刻装置包括等离子体处理室，安装在等离子体处理室中的静电卡盘，并提供待放置晶片的区域，以及围绕晶片边缘的聚焦环，在静电边缘部分 卡盘，包括：围绕晶片边缘的第一区域; 以及设置在所述晶片的底表面下方的第二区域。 第一区域具有比晶片更高的表面。

公开(公告)号：US07046500B2

公开(公告)日：2006-05-16

申请号：US11068757

申请日：2005-03-02

申请人： Byoung Hwa Lee ,  Dong Seok Park ,  Min Cheol Park ,  Sang Soo Park ,  Chang Hoon Shim ,  Kyung Nam Hwang

发明人： Byoung Hwa Lee ,  Dong Seok Park ,  Min Cheol Park ,  Sang Soo Park ,  Chang Hoon Shim ,  Kyung Nam Hwang

IPC分类号： H01G4/005 ,  H01G4/228

CPC分类号： H01G4/012 ,  H01G4/30

摘要： A laminated ceramic capacitor includes a ceramic block formed by laminating a plurality of ceramic sheets, a plurality of external electrodes formed on outer surfaces of the ceramic block facing each other, and set as a positive terminal and a negative terminal, respectively, one or more first and second internal electrodes alternately arranged within the ceramic block such that electric currents flow in opposite directions in the internal electrodes, and a plurality of withdrawing patterns for connecting the first and second internal electrodes to the external electrodes, respectively.

摘要翻译： 层叠陶瓷电容器包括通过层叠多个陶瓷片而形成的陶瓷块，形成在彼此相对的陶瓷块的外表面上的多个外部电极，分别设置为正极端子和负极端子，一个或多个 第一和第二内部电极交替地布置在陶瓷块内，使得电流在内部电极中沿相反方向流动，以及多个用于将第一和第二内部电极连接到外部电极的抽出图案。

公开(公告)号：US06940710B1

公开(公告)日：2005-09-06

申请号：US11029677

申请日：2005-01-06

申请人： Byoung Hwa Lee ,  Dong Seok Park ,  Chang Hoon Shim ,  Sang Soo Park ,  Min Cheol Park

发明人： Byoung Hwa Lee ,  Dong Seok Park ,  Chang Hoon Shim ,  Sang Soo Park ,  Min Cheol Park

IPC分类号： H01G4/232 ,  H01G4/30 ,  H01G4/06

CPC分类号： H01G4/232 ,  H01G4/30

摘要： A multilayered chip capacitor including a capacitor main body including a plurality of dielectric layers, which are laminated; at least one pair of first and second internal electrodes, each of which is formed on the corresponding one of the plural dielectric layers and includes at least one lead extended to one end of the corresponding dielectric layer; a plurality of external terminals formed on the outer surface of the capacitor main body, and respectively connected to the first and second internal electrodes through the leads; and at least one opened region, formed through the inner area of each of the first and second internal electrodes, for branching the flow of current so as to increase the offset quantity of parasitic inductances between the first and second internal electrodes.

摘要翻译： 一种多层片状电容器，其包括层叠有多个电介质层的电容器主体; 至少一对第一和第二内部电极，每个所述第一和第二内部电极形成在所述多个电介质层中的相应一个上，并且包括至少一个延伸到所述相应电介质层的一端的引线; 多个外部端子，形成在电容器主体的外表面上，分别通过引线连接到第一和第二内部电极; 以及通过第一和第二内部电极的每一个的内部区域形成的至少一个开放区域，用于分流电流，以增加第一和第二内部电极之间的寄生电感的偏移量。

公开(公告)号：US06914512B2

公开(公告)日：2005-07-05

申请号：US10461334

申请日：2003-06-16

申请人： Dong Seok Park ,  Nam Chul Kim ,  Jeong Ho Yoon ,  Byoung Hwa Lee ,  Sang Soo Park

发明人： Dong Seok Park ,  Nam Chul Kim ,  Jeong Ho Yoon ,  Byoung Hwa Lee ,  Sang Soo Park

IPC分类号： H01F19/06 ,  H01P5/10 ,  H01F27/28

CPC分类号： H01P5/10

摘要： A 3-line balun transformer includes an unbalanced port for an unbalanced signal, first and second balanced ports for balanced signals, the balanced signals being the same in level and 180 degrees out of phase with each other, a first line having its first end connected to the unbalanced port and its second end connected to ground, a second line arranged in parallel with the first line while being spaced apart from the first line, the second line having its first end and its second end connected to the first balanced port, and a third line arranged in parallel with the second line while being spaced apart from the second, the third line having its first end connected to the first end of the second line and its second end connected to the second balanced port.

摘要翻译： 3线平衡 - 不平衡变压器包括用于不平衡信号的不平衡端口，用于平衡信号的第一和第二平衡端口，平衡信号彼此相同且相位相差180度，其第一端连接 连接到不平衡端口，其第二端连接到地，第二线与第一线平行布置，同时与第一线间隔开，第二线具有其第一端并且其第二端连接到第一平衡端口，以及 第三线与第二线平行布置，同时与第二线隔开，第三线的第一端连接到第二线的第一端，其第二端连接到第二平衡端口。

公开(公告)号：US06885259B2

公开(公告)日：2005-04-26

申请号：US10623594

申请日：2003-07-22

申请人： Byoung Hwa Lee ,  Nam Chul Kim ,  James Mike Peters ,  Myung Pyo Jun ,  Jeong Ho Yoon ,  Ian Lee ,  Dong Seok Park ,  Sang Soo Park

发明人： Byoung Hwa Lee ,  Nam Chul Kim ,  James Mike Peters ,  Myung Pyo Jun ,  Jeong Ho Yoon ,  Ian Lee ,  Dong Seok Park ,  Sang Soo Park

IPC分类号： H04B1/44 ,  H01P1/203 ,  H01P1/213 ,  H01P5/02

CPC分类号： H01P5/02 ,  H01P1/213

摘要： Disclosed is a matching circuit of a laminated duplexer connected to an antenna terminal while being connected between transmitting and receiving filters to match the transmitting and receiving filters with the antenna terminal, the matching circuit being configured to reduce the physical length of each conductor pattern thereof, thereby being capable of achieving an improved miniaturization thereof. The matching circuit includes a transmitting matching unit constituted by a conductor pattern electrically connected to an antenna electrode connected to the antenna terminal while being electrically connected to the transmitting filter, a first ground electrode vertically spaced apart from the conductor pattern, a receiving matching unit constituted by a conductor pattern electrically connected to the antenna electrode and the receiving filter, and a second ground electrode vertically spaced apart from the conductor pattern of the receiving matching unit. A laminated duplexer provided with the matching circuit is also disclosed. In accordance with the configuration of the matching circuit, it is possible to achieve a reduction in insertion loss, an improvement in the reflection characteristics of an associated antenna, and, thus, an improvement in bandpass characteristics.

摘要翻译： 公开了一种连接到天线端子的层叠双工器的匹配电路，同时连接在发射和接收滤波器之间以将发射和接收滤波器与天线端子匹配，匹配电路被配置为减小其每个导体图案的物理长度， 从而能够实现其小型化。 匹配电路包括发射匹配单元，其由与连接到天线端子的天线电极电连接的导体图案构成，同时电连接到发射滤波器，与导体图案垂直间隔开的第一接地电极，构成的接收匹配单元 通过与天线电极和接收滤波器电连接的导体图案和与接收匹配单元的导体图案垂直间隔开的第二接地电极。 还公开了配备有匹配电路的层压双工器。 根据匹配电路的结构，可以实现插入损耗的降低，相关天线的反射特性的提高，从而提高带通特性。

公开(公告)号：US06793657B2

公开(公告)日：2004-09-21

申请号：US09949583

申请日：2001-09-10

申请人： Choon Ki Lee ,  Cheol Sang Kim ,  Sung Pil Choi ,  Duc Soo Moon ,  Sang Soo Park ,  Seayoung Ahn

发明人： Choon Ki Lee ,  Cheol Sang Kim ,  Sung Pil Choi ,  Duc Soo Moon ,  Sang Soo Park ,  Seayoung Ahn

IPC分类号： A61B1770

CPC分类号： A61B17/7052 ,  A61B17/7032

摘要： A spine-fixing apparatus includes a plurality of spine screw members fixed to a spine in a predetermined interval, a pair of rods coupled to the spine screw members for supporting the spine, a plurality of fixing nuts coupled to the spine screw members, and a plurality of pressing pieces interposed between the fixing nuts and the spine screw members for pressing and fixing the rods.

摘要翻译： 脊柱固定装置包括以预定间隔固定到脊柱的多个脊柱螺钉构件，连接到用于支撑脊柱的脊柱螺钉构件的一对杆，联接到脊螺钉构件的多个固定螺母，以及 多个压紧片介于固定螺母和脊螺纹构件之间，用于按压和固定杆。

公开(公告)号：US20170125128A1

公开(公告)日：2017-05-04

申请号：US15207774

申请日：2016-07-12

申请人： JI-SANG LEE ,  SANG-SOO PARK ,  DONG-KYO SHIM

发明人： JI-SANG LEE ,  SANG-SOO PARK ,  DONG-KYO SHIM

IPC分类号： G11C29/56 ,  G11C8/10 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C7/10

CPC分类号： G11C29/1201 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/12 ,  G11C7/14 ,  G11C7/222 ,  G11C8/10 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C27/02 ,  G11C29/42 ,  G11C29/50012 ,  G11C29/52 ,  G11C29/56008 ,  G11C2029/0411 ,  G11C2029/5004 ,  G11C2211/5642

摘要： A nonvolatile memory device with a memory cell array including a plurality of memory cells coupled to first through M-th wordlines and first through N-th bitlines (M>2, N>2), and a page buffer circuit including first through N-th page buffers that are coupled to the first through N-th bitlines, respectively, and generate first through N-th output data, respectively. A K-th page buffer includes first through L-th latches which generate read data by sampling a voltage of a K-th output line, which is discharged through a K-th bitline, at different sampling timings after a read voltage is applied to a P-th wordline (K≦N, L>1, P≦M). The K-th page buffer outputs the first output data if an error in the read data of the first latch is correctable.

公开(公告)号：US20170123724A1

公开(公告)日：2017-05-04

申请号：US15336014

申请日：2016-10-27

申请人： SANG-SOO PARK ,  DONG-KYO SHIM

发明人： SANG-SOO PARK ,  DONG-KYO SHIM

IPC分类号： G06F3/06 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  G11C16/16

CPC分类号： G06F3/0656 ,  G06F3/0604 ,  G06F3/0685 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/3459 ,  G11C2211/5642 ,  G11C2211/5643 ,  G11C2211/5644

摘要： A memory device is provided as follows. A memory cell array includes a plurality of memory cells, and the plurality of memory cells are divided into a first memory group and a second memory group. A first page buffer group is coupled to the first memory group and includes a plurality of first page buffers. A second page buffer group is coupled to the second memory group and includes a plurality of second page buffers. The first page buffer group performs a first data processing operation on data stored in the first page buffer group and stores a result of the first data processing operation. The second page buffer group performs a second data processing operation on data stored in the second page buffer group and stores a result of the second data processing operation. The first and second data processing operations are performed at substantially the same.

公开(公告)号：US09099242B2

公开(公告)日：2015-08-04

申请号：US13588696

申请日：2012-08-17

申请人： Young Ghyu Ahn ,  Sang Soo Park ,  Min Cheol Park ,  Se Hwa Jeong

发明人： Young Ghyu Ahn ,  Sang Soo Park ,  Min Cheol Park ,  Se Hwa Jeong

IPC分类号： H05K1/16 ,  H01G4/005 ,  H05K1/02 ,  H01G4/30

CPC分类号： H01G4/005 ,  H01G4/30 ,  H05K1/0271 ,  H05K1/111 ,  H05K3/3442 ,  H05K2201/09427 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/2045 ,  Y02P70/611

摘要： A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; external electrodes formed to cover both end portions of the ceramic body in a length direction; an active layer in which the internal electrodes are disposed in an opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; and upper and lower cover layers formed on upper and lower portions of the active layer in a thickness direction, the lower cover layer having a thickness greater than that of the upper cover layer.

摘要翻译： 层叠芯片电子部件包括：陶瓷体，其包括内部电极和电介质层; 形成为在长度方向上覆盖陶瓷体的两端部的外部电极; 其中内部电极以相对的方式设置在其间插入电介质层的有源层以形成电容; 以及在有源层的厚度方向的上部和下部形成的上部和下部覆盖层，所述下部覆盖层的厚度大于上部覆盖层的厚度。

公开(公告)号：US08638543B2

公开(公告)日：2014-01-28

申请号：US13588876

申请日：2012-08-17

申请人： Young Ghyu Ahn ,  Min Cheol Park ,  Doo Young Kim ,  Sang Soo Park

发明人： Young Ghyu Ahn ,  Min Cheol Park ,  Doo Young Kim ,  Sang Soo Park

IPC分类号： H01G4/06 ,  H01G4/005

CPC分类号： H01G4/30 ,  B65B9/04 ,  B65B15/04 ,  H01G2/065 ,  H01G4/012 ,  H01G4/12 ,  H05K1/181 ,  H05K2201/10015

摘要： A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; first and second external electrodes formed to cover both end portions of the ceramic body in a length direction; an active layer in which the internal electrodes are disposed in an opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; upper and lower cover layers formed on upper and lower portions of the active layer in a thickness direction, the lower cover layer having a thickness greater than that of the upper cover layer; and additional electrode layers disposed irrespective of a formation of capacitance within the lower cover layer.

摘要翻译： 层叠芯片电子部件包括：陶瓷体，其包括内部电极和电介质层; 形成为在长度方向上覆盖陶瓷体的两端部的第一外部电极和第二外部电极; 其中内部电极以相对的方式设置在其间插入电介质层的有源层以形成电容; 上下层形成在有源层的厚度方向的上部和下部上，下覆盖层的厚度大于上覆盖层的厚度; 以及与下覆盖层内的电容的形成无关地设置的附加电极层。