公开(公告)号：US20150370311A1

公开(公告)日：2015-12-24

申请号：US14310908

申请日：2014-06-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko Eckert ,  Manish Arora ,  Indrani Paul

IPC: G06F1/32 ,  G06N5/04

CPC classification number: G06F1/3296 ,  G06F1/3228 ,  G06F1/3287 ,  G06F1/3293 ,  G06N5/04 ,  Y02D10/171 ,  Y02D50/20

Abstract: Power gating logic detects a transition of a component of a processing device into an idle state. In response to detecting the transition, the entry/exit power gating logic selectively implements one or more entry prediction techniques for power gating the component based on estimates of reliability of the entry prediction techniques. The entry/exit power gating logic also selectively implements one or more exit prediction techniques for exiting the power gated state based on estimates of reliability of the exit prediction techniques.

Abstract translation: 电源门控逻辑检测处理设备的组件转换到空闲状态。 响应于检测到转换，入口/出口功率门控逻辑基于入口预测技术的可靠性的估计，选择性地实现用于功率门控组件的一个或多个入口预测技术。 入口/出口电力门控逻辑还基于对退出预测技术的可靠性的估计，选择性地实现一个或多个退出预测技术以退出电力门控状态。

公开(公告)号：US20150355692A1

公开(公告)日：2015-12-10

申请号：US14297208

申请日：2014-06-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Indrani Paul ,  Vignesh Trichy Ravi ,  Manish Arora ,  Srilatha Manne

IPC: G06F1/20 ,  G06F9/50 ,  G06F11/30 ,  G06F1/32

CPC classification number: G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/324 ,  G06F9/5094 ,  G06F11/3058 ,  G06F11/3409 ,  G06F11/3447 ,  Y02D10/126 ,  Y02D10/22

Abstract: A method includes controlling active frequency states of a plurality of heterogeneous processing units based on frequency sensitivity metrics indicating performance coupling between different types of processing units in the plurality of heterogeneous processing units. A processor includes a plurality of heterogeneous processing units and a performance controller to control active frequency states of the plurality of heterogeneous processing units based on frequency sensitivity metrics indicating performance coupling between different types of processing units in the plurality of heterogeneous processing units. The active frequency state of a first type of processing unit in the plurality of heterogeneous processing units is controlled based on a first activity metric associated with a first type of processing unit and a second activity metric associated with a second type of processing unit.

Abstract translation: 一种方法包括基于指示多个异构处理单元中的不同类型的处理单元之间的性能耦合的频率灵敏度度量来控制多个异构处理单元的活动频率状态。 处理器包括多个异构处理单元和性能控制器，用于基于指示多个异构处理单元中的不同类型的处理单元之间的性能耦合的频率灵敏度度量来控制多个异构处理单元的有效频率状态。 基于与第一类型处理单元相关联的第一活动度量和与第二类型处理单元相关联的第二活动度量来控制多个异构处理单元中的第一类型处理单元的活动频率状态。

公开(公告)号：US20150186160A1

公开(公告)日：2015-07-02

申请号：US14146588

申请日：2014-01-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Arora ,  Indrani Paul ,  Yasuko Eckert ,  Nuwan S. Jayasena ,  Srilatha Manne

IPC: G06F9/445 ,  G06F11/34 ,  G06F12/08

CPC classification number: G06F11/3423 ,  G06F1/3243 ,  G06F11/3452 ,  G06F12/0804 ,  G06F12/0864 ,  G06F2212/601 ,  Y02D10/152 ,  Y02D10/34 ,  Y02D50/20

Abstract: Durations of active performance states of components of a processing system can be predicted based on one or more previous durations of an active state of the components. One or more entities in the processing system such as processor cores or caches can be configured based on the predicted durations of the active state of the components. Some embodiments configure a first component in a processing system based on a predicted duration of an active state of a second component of the processing system. The predicted duration is predicted based on one or more previous durations of an active state of the second component.

Abstract translation: 可以基于组件的活动状态的一个或多个先前持续时间来预测处理系统的组件的主动性能状态的持续时间。 可以基于组件的活动状态的预测持续时间来配置处理系统中的一个或多个实体，例如处理器核心或高速缓存。 一些实施例基于处理系统的第二组件的活动状态的预测持续时间来配置处理系统中的第一组件。 基于第二组件的活动状态的一个或多个先前持续时间预测预测持续时间。

公开(公告)号：US20250112470A1

公开(公告)日：2025-04-03

申请号：US18478346

申请日：2023-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： David King Wai Li ,  Indrani Paul

IPC: H02J4/00 ,  G01R19/165

Abstract: The disclosed device includes power circuits that can communicate with a control circuit. In response to a power circuit communicating a low efficiency state, the control circuit can redistribute at least a portion of a load of the power circuit to one or more other power circuits. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US12181944B2

公开(公告)日：2024-12-31

申请号：US17562854

申请日：2021-12-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander J. Branover ,  Thomas J. Gibney ,  Stephen V. Kosonocky ,  Mihir Shaileshbhai Doctor ,  John P. Petry ,  Indrani Paul ,  Benjamin Tsien ,  Christopher T. Weaver

IPC: G06F1/3206

Abstract: A method and apparatus for managing power states in a computer system includes, responsive to an event received by a processor, powering up a first circuitry. Responsive to the event not being serviceable by the first circuitry, powering up at least a second circuitry of the computer system to service the event.

公开(公告)号：US12130692B2

公开(公告)日：2024-10-29

申请号：US17993562

申请日：2022-11-23

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Karthik Rao ,  Indrani Paul ,  Donny Yi ,  Oleksandr Khodorkovsky ,  Leonardo De Paula Rosa Piga ,  Wonje Choi ,  Dana G. Lewis ,  Sriram Sambamurthy

IPC: G06F1/32 ,  G06F1/3287

CPC classification number: G06F1/3287

Abstract: An apparatus includes a processor, a sleep state duration prediction module, and a system management unit. The sleep state duration prediction module is configured to predict a sleep state duration for component of the processing device. The system management unit is to transition the component into a sleep state selected from a plurality of sleep states based on a comparison of the predicted sleep state duration to at least one duration threshold. Each sleep state of the plurality of sleep states is a lower power state than a previous sleep state of the plurality of sleep states.

公开(公告)号：US12130690B2

公开(公告)日：2024-10-29

申请号：US18316865

申请日：2023-05-12

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Alexander J. Branover ,  Christopher T. Weaver ,  Benjamin Tsien ,  Indrani Paul ,  Mihir Shaileshbhai Doctor ,  Thomas J. Gibney ,  John P. Petry ,  Dennis Au ,  Oswin Hall

IPC: G06F1/32 ,  G06F1/3209 ,  G06F1/3234

CPC classification number: G06F1/3265 ,  G06F1/3209 ,  G06F1/3275

Abstract: A method and system for operating in a single display mode operation and a dual pipe mode of operation is disclosed. The method and system includes operating in a dual pipe mode of operation in which each display pipe transmits data from a respective buffer to an associated display. The method and system further includes operating in a single display mode of operation in which one display pipe transmits data from a plurality of buffers to an associated display.

公开(公告)号：US12072754B2

公开(公告)日：2024-08-27

申请号：US17485199

申请日：2021-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander J. Branover ,  Christopher T. Weaver ,  Indrani Paul ,  Benjamin Tsien ,  Mihir Shaileshbhai Doctor ,  Stephen V. Kosonocky ,  John P. Petry ,  Thomas J. Gibney

IPC: G06F1/00 ,  G06F1/3296

CPC classification number: G06F1/3296

Abstract: A method and apparatus for managing a controller includes indicating, by a processor of a first device, to the controller of a second device to enter a second power state from a first power state. The controller of the second device responds to the processor of the first device with a confirmation. The processor of the first device transmits a signal to the controller of the second device to enter the second power state. Upon receiving a wake event, the controller of the second device exits the second device from the second power state to the first power state.

公开(公告)号：US11886878B2

公开(公告)日：2024-01-30

申请号：US16712891

申请日：2019-12-12

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Sukesh Shenoy ,  Adam N. C. Clark ,  Indrani Paul

IPC: G06F1/00 ,  G06F9/30 ,  G06F9/48 ,  G06F1/3203 ,  G06F9/38

CPC classification number: G06F9/30083 ,  G06F1/3203 ,  G06F9/3877 ,  G06F9/4843 ,  G06F2009/3883

Abstract: An integrated coprocessor such as an accelerated processing unit (APU) generates commands for execution on a discrete coprocessor such as a discrete graphics processing unit (dGPU). Power distribution circuitry selectively provides power to the APU and the dGPU based on characteristics of workloads executing on the APU and the dGPU and based on a platform power limit that is shared by the APU and the dGPU. In some cases, the power distribution circuitry determines a first power provided to the APU and a second power provided to the dGPU. The power distribution circuitry increases the second power provided to the dGPU in response to a sum of the first and second powers being less than the platform power limit. In some cases, the power distribution circuitry modifies the power provided to the APU, the dGPU, or both in response to changes in temperatures measured by a set of sensors.

公开(公告)号：US20240004453A1

公开(公告)日：2024-01-04

申请号：US17854858

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Ashwini Chandrashekhara Holla ,  Alexander S. Duenas ,  Xinzhe Li ,  Indrani Paul ,  Karthik Rao

IPC: G06F1/324

CPC classification number: G06F1/324

Abstract: Methods and systems are disclosed for managing the power consumed by cores of a system on chip (SoC). Techniques disclosed include obtaining application information that is indicative of an application being executed on the cores, detecting a workload associated with the application, and limiting one or more operating frequencies of the cores responsive to the detection of the workload. Techniques disclosed also include profiling the detected workload and limiting the one or more operating frequencies of the cores based on the profiling.