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    PE-SiN spacer profile for C2 SAC isolation window
    81.
    发明授权
    PE-SiN spacer profile for C2 SAC isolation window 有权
    用于C2 SAC隔离窗的PE-SiN间隔件

    公开(公告)号：US06225203B1

    公开(公告)日：2001-05-01

    申请号：US09304334

    申请日：1999-05-03

    申请人： Jen-Cheng Liu ,  Jen-Shiang Leu ,  Chia-Shiung Tsai

    发明人： Jen-Cheng Liu ,  Jen-Shiang Leu ,  Chia-Shiung Tsai

    IPC分类号： H01L21302

    CPC分类号： H01L27/10855 ,  H01L21/31116 ,  H01L21/3185 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10885

    摘要： A method of forming a PE-CVD silicon nitride spacer having a good profile in the fabrication of a self-aligned contact wherein a two-step etching process forms the spacer is described. Semiconductor device structures are formed on a semiconductor substrate. A layer of silicon nitride is deposited by plasma-enhanced chemical vapor deposition over the surface of the substrate and overlying the semiconductor device structures. The silicon nitride layer is etched away using a two-step etching process to leave silicon nitride spacers on the side surfaces of the semiconductor device structures. The two-step process comprises a first etching away of 70% of the silicon nitride layer using Cl2/He chemistry and a second etching away of the remaining silicon nitride on top surface of the semiconductor device strucutures using SF6/CHF3/He chemistry.

    摘要翻译： 描述了在制造自对准接触中具有良好外形的PE-CVD氮化硅间隔物的方法，其中两步蚀刻工艺形成间隔物。 半导体器件结构形成在半导体衬底上。 通过等离子体增强化学气相沉积在衬底的表面上并覆盖半导体器件结构来沉积氮化硅层。 使用两步蚀刻工艺蚀刻掉氮化硅层，以在半导体器件结构的侧表面上留下氮化硅间隔物。 两步法包括使用Cl2 / He化学法首先蚀刻掉70％的氮化硅层，并且使用SF6 / CHF3 / He化学法在半导体器件结构的顶表面上第二次蚀刻剩余的氮化硅。

    Isolation trench with a rounded top edge using an etch buffer layer
    82.
    发明授权
    Isolation trench with a rounded top edge using an etch buffer layer 失效
    使用蚀刻缓冲层的具有圆形顶部边缘的隔离沟槽

    公开(公告)号：US5674775A

    公开(公告)日：1997-10-07

    申请号：US803466

    申请日：1997-02-20

    申请人： Chin-Hsiung Ho ,  Chia-Shiung Tsai ,  Cheng-Kai Liu ,  Chaochieh Tsai

    发明人： Chin-Hsiung Ho ,  Chia-Shiung Tsai ,  Cheng-Kai Liu ,  Chaochieh Tsai

    IPC分类号： H01L21/308 ,  H01L21/762 ,  H01L21/76

    CPC分类号： H01L21/76232 ,  H01L21/3086 ,  Y10S148/05

    摘要： The present invention provides a method of manufacturing a trench having rounded top corners 28 in a substrate. The rounded top edges allow the formation of a gate oxide with a uniform thickness around the trench thereby reducing parasitic field FET problems. The method begins by forming a pad layer 14 over a semiconductor substrate 10. Next, an insulating layer 18 composed of silicon nitride is formed over the pad layer 14. A first opening 19 is formed in the insulating layer 18 and the pad layer 14 exposing the surface of the substrate. The first opening is defined by sidewalls of the pad layer 14 and of the insulating layer 18. An etch buffer layer 20 composed of polysilicon is formed over the resultant surface. In one etch step, the etch buffer layer 20 is anisotropically etched forming spacers 22 on the sidewalls of the pad layer 14 and of the insulating layer 18. The same etch step continues by etching the spacers 22 and the exposed substrate in the first opening 19 thereby forming a trench 26 in the substrate 10. Because the etch has to etch through the spacers before it reached the substrate, the trench 26 has rounded top edges 28 near the pad layer 14. Lastly, the pad layer 14 and the first insulating layer 18 are removed thereby forming the trench 26 with rounded top edges 28.

    摘要翻译： 本发明提供一种制造在衬底中具有圆形顶角28的沟槽的方法。 圆形顶部边缘允许在沟槽周围形成均匀厚度的栅极氧化物，从而减少寄生场FET问题。 该方法开始于在半导体衬底10上形成衬垫层14.接下来，在衬底层14上形成由氮化硅构成的绝缘层18.第一开口19形成在绝缘层18中，衬垫层14暴露 衬底的表面。 第一开口由衬垫层14和绝缘层18的侧壁限定。在所得表面上形成由多晶硅构成的蚀刻缓冲层20。 在一个蚀刻步骤中，蚀刻缓冲层20被各向异性蚀刻，在衬垫层14和绝缘层18的侧壁上形成间隔物22.通过在第一开口19中蚀刻间隔物22和暴露的衬底，继续相同的蚀刻步骤 从而在衬底10中形成沟槽26.因为蚀刻必须在其到达衬底之前蚀刻穿过间隔物，所以沟槽26在焊盘层14附​​近具有圆形的顶部边缘28.最后，焊盘层14和第一绝缘层 18被去除，从而形成具有圆形顶部边缘28的沟槽26。

    Silicon wafer strength enhancement
    83.
    发明授权
    Silicon wafer strength enhancement 有权
    硅片强度提高

    公开(公告)号：US09123671B2

    公开(公告)日：2015-09-01

    申请号：US12982275

    申请日：2010-12-30

    申请人： Chi-Ming Chen ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ho-Yung David Hwang ,  Alexander Kalnitsky

    发明人： Chi-Ming Chen ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ho-Yung David Hwang ,  Alexander Kalnitsky

    IPC分类号： H01L21/322

    CPC分类号： H01L21/3225

    摘要： Provided is a method of fabricating a semiconductor device. The method includes: receiving a silicon wafer that contains oxygen; forming a zone in the silicon wafer, the zone being substantially depleted of oxygen; causing a nucleation process to take place in the silicon wafer to form oxygen nuclei in a region of the silicon wafer outside the zone; and growing the oxygen nuclei into defects. Also provided is an apparatus that includes a silicon wafer. The silicon wafer includes: a first portion that is substantially free of oxygen, the first portion being disposed near a surface of the silicon wafer; and a second portion that contains oxygen; wherein the second portion is at least partially surrounded by the first portion.

    摘要翻译： 提供一种制造半导体器件的方法。 该方法包括：接收含有氧的硅晶片; 在硅晶片中形成区域，该区域基本上耗尽氧气; 导致在硅晶片中发生成核过程，以在区域外的硅晶片的区域中形成氧核; 并将氧原子生长成缺陷。 还提供了一种包括硅晶片的装置。 硅晶片包括：基本上不含氧的第一部分，第一部分设置在硅晶片的表面附近; 和含有氧的第二部分; 其中所述第二部分至少部分地被所述第一部分包围。

    MRAM device and fabrication method thereof
    84.
    发明授权
    MRAM device and fabrication method thereof 有权
    MRAM器件及其制造方法

    公开(公告)号：US08921959B2

    公开(公告)日：2014-12-30

    申请号：US13190966

    申请日：2011-07-26

    申请人： Fu-Ting Sung ,  Shih-Chang Liu ,  Chia-Shiung Tsai

    发明人： Fu-Ting Sung ,  Shih-Chang Liu ,  Chia-Shiung Tsai

    IPC分类号： H01L29/82 ,  G11C11/00 ,  H01L21/00 ,  H01L43/12 ,  H01L43/08

    CPC分类号： H01L43/12 ,  H01L43/08

    摘要： According to an embodiment, a magnetoresistive random access memory (MRAM) device comprises a bottom electrode, a stack, a dielectric material, a dielectric layer, and a conductive material. The bottom electrode is over a substrate, and the stack is over the bottom electrode. The stack comprises a magnetic tunnel junction (MTJ) and a top electrode. The dielectric material is along a sidewall of the stack, and the dielectric material has a height greater than a thickness of the MTJ and less than a stack height. The dielectric layer is over the stack and the dielectric material. The conductive material extends through the dielectric layer to the top electrode of the stack.

    摘要翻译： 根据实施例，磁阻随机存取存储器（MRAM）器件包括底部电极，堆叠，电介质材料，电介质层和导电材料。 底部电极在衬底上方，并且堆叠层在底部电极之上。 堆叠包括磁性隧道结（MTJ）和顶部电极。 介电材料沿着堆叠的侧壁，并且电介质材料具有高于MTJ的厚度并小于堆叠高度的高度。 电介质层在电池堆和电介质材料之上。 导电材料通过电介质层延伸到堆叠的顶部电极。

    MEMS structures and methods for forming the same
    86.
    发明授权
    MEMS structures and methods for forming the same 有权
    MEMS结构及其形成方法

    公开(公告)号：US08836055B2

    公开(公告)日：2014-09-16

    申请号：US13250078

    申请日：2011-09-30

    申请人： Lung Yuan Pan ,  Lan-Lin Chao ,  Chia-Shiung Tsai

    发明人： Lung Yuan Pan ,  Lan-Lin Chao ,  Chia-Shiung Tsai

    IPC分类号： H01L31/115

    CPC分类号： H01G5/18 ,  B81B3/001 ,  B81B2201/0221 ,  H01L28/60

    摘要： A device includes a micro-electro-mechanical system (MEMS) device, which includes a movable element and a fixed element. The movable element and the fixed element form two capacitor plates of a capacitor, with an air-gap between the movable element and the fixed element acting as a capacitor insulator of the capacitor. At least one of the movable element and the fixed element has a rugged surface.

    摘要翻译： 一种装置包括微电子机械系统（MEMS）装置，其包括可移动元件和固定元件。 可移动元件和固定元件形成电容器的两个电容器板，可动元件和固定元件之间的气隙用作电容器的电容器绝缘体。 可移动元件和固定元件中的至少一个具有粗糙的表面。

    Methods of bonding caps for MEMS devices
    87.
    发明授权
    Methods of bonding caps for MEMS devices 有权
    MEMS器件封装方法

    公开(公告)号：US08790946B2

    公开(公告)日：2014-07-29

    申请号：US13365043

    申请日：2012-02-02

    申请人： Xin-Hua Huang ,  Ping-Yin Liu ,  Li-Cheng Chu ,  Yuan-Chih Hsieh ,  Lan-Lin Chao ,  Chun-Wen Cheng ,  Chia-Shiung Tsai

    发明人： Xin-Hua Huang ,  Ping-Yin Liu ,  Li-Cheng Chu ,  Yuan-Chih Hsieh ,  Lan-Lin Chao ,  Chun-Wen Cheng ,  Chia-Shiung Tsai

    IPC分类号： H01L21/52

    CPC分类号： B23K20/002 ,  B23K20/023

    摘要： A method includes bonding a first bond layer to a second bond layer through eutectic bonding. The step of bonding includes heating the first bond layer and the second bond layer to a temperature higher than a eutectic temperature of the first bond layer and the second bond layer, and performing a pumping cycle. The pumping cycle includes applying a first force to press the first bond layer and the second bond layer against each other. After the step of applying the first force, a second force lower than the first force is applied to press the first bond layer and the second bond layer against each other. After the step of applying the second force, a third force higher than the second force is applied to press the first bond layer and the second bond layer against each other.

    摘要翻译： 一种方法包括通过共晶接合将第一接合层结合到第二接合层。 接合步骤包括将第一接合层和第二接合层加热至高于第一接合层和第二接合层的共晶温度的温度，并进行泵送循环。 泵送循环包括施加第一力以将第一接合层和第二接合层相互挤压。 在施加第一力的步骤之后，施加比第一力小的第二力以将第一接合层和第二接合层相互挤压。 在施加第二力的步骤之后，施加比第二力高的第三力以将第一接合层和第二接合层相互挤压。

    Method to Form a CMOS Image Sensor
    88.
    发明申请
    Method to Form a CMOS Image Sensor 有权
    形成CMOS图像传感器的方法

    公开(公告)号：US20140061738A1

    公开(公告)日：2014-03-06

    申请号：US13602494

    申请日：2012-09-04

    申请人： Chung Chien Wang ,  Yeur-Luen Tu ,  Cheng-Ta Wu ,  Jiech-Fun Lu ,  Chun-Wei Chang ,  Wang-Pen Mo ,  Jhy-Jyi Sze ,  Chia-Shiung Tsai

    发明人： Chung Chien Wang ,  Yeur-Luen Tu ,  Cheng-Ta Wu ,  Jiech-Fun Lu ,  Chun-Wei Chang ,  Wang-Pen Mo ,  Jhy-Jyi Sze ,  Chia-Shiung Tsai

    IPC分类号： H01L31/0216

    CPC分类号： H01L21/266 ,  H01L27/14689

    摘要： The present disclosure relates to a method and composition to limit crystalline defects introduced in a semiconductor device during ion implantation. A high-temperature low dosage implant is performed utilizing a tri-layer photoresist which maintains the crystalline structure of the semiconductor device while limiting defect formation within the semiconductor device. The tri-layer photoresist comprises a layer of spin-on carbon deposited onto a substrate, a layer of silicon containing hard-mask formed above the layer of spin-on carbon, and a layer of photoresist formed above the layer of silicon containing hard-mask. A pattern formed in the layer of photoresist is sequentially transferred to the silicon containing hard-mask, then to the spin-on carbon, and defines an area of the substrate to be selectively implanted with ions.

    摘要翻译： 本发明涉及在离子注入期间限制在半导体器件中引入的结晶缺陷的方法和组合物。 使用保持半导体器件的晶体结构同时限制半导体器件内的缺陷形成的三层光致抗蚀剂进行高温低剂量注入。 三层光致抗蚀剂包括沉积在基底上的旋涂碳层，在旋涂碳层上方形成的含硅的硬掩模层，以及形成在含硅硬质层的硅层之上的光致抗蚀剂层， 面具。 形成在光致抗蚀剂层上的图案被顺序地转移到含硅的硬掩模，然后转移到旋涂碳上，并且限定要选择性地注入离子的衬底区域。