公开(公告)号：US20100060906A1

公开(公告)日：2010-03-11

申请号：US12206026

申请日：2008-09-08

申请人： Wen-Yuh Jywe ,  Chien-Hung Liu ,  Yi-Tsung Li ,  Tung-Hsien Hsieh ,  Tung-Hui Hsu ,  Hung-Shu Wang

发明人： Wen-Yuh Jywe ,  Chien-Hung Liu ,  Yi-Tsung Li ,  Tung-Hsien Hsieh ,  Tung-Hui Hsu ,  Hung-Shu Wang

IPC分类号： G01B11/00

CPC分类号： G01B11/272 ,  B23Q17/24 ,  B23Q2230/002

摘要： Means for measuring a working machine's structural deviation from five reference axes includes a main sensing body bonded with a main axis of the working machine (or controlled to revolve), and a lighting unit set around the main sensing body to circle about the main sensing body with a fixed radius (or the lighting unit radiates a light on the main sensing body from that radial distance and circles along with the main sensing body) such that as soon as the main sensing body has detected an optical signal, it is converted to an error signal informing of the working machine's structural deviation in two or three dimensional displacement.

摘要翻译： 用于测量工作机械与五个参考轴的结构偏差的装置包括与工作机的主轴（或控制旋转）结合的主感测体，以及围绕主感测体围绕主感测体环绕的照明单元 具有固定半径（或者照明单元从该径向距离辐射主感测体上的光并与主感测体一起旋转），使得一旦主感测体检测到光信号，就将其转换为 误差信号通知工作机械在二维或三维位移中的结构偏差。

公开(公告)号：US20090212353A1

公开(公告)日：2009-08-27

申请号：US12434828

申请日：2009-05-04

申请人： Chin-Hsien Chen ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shou-Wei Huang

发明人： Chin-Hsien Chen ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shou-Wei Huang

IPC分类号： H01L29/792

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/7881 ,  H01L29/792

摘要： A non-volatile memory includes a substrate having two openings, a stacked gate structure disposed on the substrate between the two openings, a liner disposed on a bottom of each of the two openings and parts of a sidewall of each of the two openings, a second conductive layer disposed on the liner at the bottom of each of the two openings, and a third conductive layer on the second conductive layer and the liner. The stacked gate structure includes a first dielectric layer, a charge storage layer, a second dielectric layer, and a first conductive layer. The liner has a top surface lower than that of the substrate. The second conductive layer has a top surface co-planar with that of the liner. The third conductive layer has a top surface at least co-planar with that of the substrate and lower than that of the first dielectric layer.

摘要翻译： 非易失性存储器包括具有两个开口的衬底，设置在两个开口之间的衬底上的堆叠栅极结构，设置在两个开口中的每一个的底部和两个开口中的每一个的侧壁的一部分的衬垫， 设置在两个开口中的每一个的底部的衬垫上的第二导电层，以及在第二导电层和衬垫上的第三导电层。 层叠栅极结构包括第一介电层，电荷存储层，第二介电层和第一导电层。 衬垫具有比衬底更低的顶表面。 第二导电层具有与衬垫的顶表面共面的顶表面。 第三导电层具有至少与基底的共面的顶表面，并且低于第一介电层的顶表面。

公开(公告)号：US07572691B2

公开(公告)日：2009-08-11

申请号：US11435458

申请日：2006-05-16

申请人： Chin-Hsien Chen ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shou-Wei Huang

发明人： Chin-Hsien Chen ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shou-Wei Huang

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/7881 ,  H01L29/792

摘要： A method of fabricating a non-volatile memory is provided. First, two openings are formed on a substrate. A stacked gate structure comprising a first dielectric layer, a charge storage layer, a second dielectric layer and a first conductive layer is formed on the substrate between the two openings. A liner is formed on a bottom and a portion of a sidewall of the tow openings, wherein a top surface of the liner is lower than that of the substrate. A second conductive layer is formed on the liner at the bottom of the two openings, wherein a top surface of the second conductive layer is co-planar with that of the liner. A third conductive layer is formed on the second conductive layer and the liner, wherein a top surface of the third conductive layer is co-planar with that of the substrate and lower than that of the first dielectric layer.

摘要翻译： 提供了一种制造非易失性存储器的方法。 首先，在基板上形成两个开口。 在两个开口之间的基板上形成包括第一电介质层，电荷存储层，第二电介质层和第一导电层的堆叠栅极结构。 衬套形成在丝束开口的侧壁的底部和一部分上，其中衬垫的顶表面低于衬底的顶表面。 第二导电层形成在两个开口的底部的衬垫上，其中第二导电层的顶表面与衬垫的顶表面共面。 第三导电层形成在第二导电层和衬垫上，其中第三导电层的顶表面与衬底的顶表面平行，并且低于第一介电层的顶表面。

公开(公告)号：US20090069046A1

公开(公告)日：2009-03-12

申请号：US11853845

申请日：2007-09-12

申请人： Chien-Kun Liu ,  Chien-Hung Liu

发明人： Chien-Kun Liu ,  Chien-Hung Liu

IPC分类号： H04B1/38

CPC分类号： G06F1/1626 ,  G06F1/1684 ,  G06F1/1694 ,  G06F3/0485 ,  G06F2200/1637

摘要： A virtual paper reading device comprises a virtual paper reading device for viewing a document from a screen through a mobile device; wherein the document to be read has a size as an original size and an original printed page; a 3 axial sensor in the mobile device for sensing moving direction of the mobile device; a key set for adjusting a size of the document to be presented and a present area of the document to be presented; and an application software for receiving the moving direction message from the 3 axial sensor and adjusting signals from the key set so as to adjust a present area and a size of the document to be presented on the screen of the mobile device. The user can read the message from the document easily and conveniently.

摘要翻译： 虚拟纸张读取装置包括用于通过移动装置从屏幕观看文档的虚拟纸阅读装置; 其中待读取的文档具有作为原始大小和原始打印页面的大小; 移动装置中的3轴向传感器，用于感测移动装置的移动方向; 用于调整要呈现的文档的大小和要呈现的文档的当前区域的键集合; 以及用于从所述3轴传感器接收所述移动方向消息并从所述密钥组调整信号的应用软件，以便调整要呈现在所述移动设备的屏幕上的所述文档的当前区域和大小。 用户可以方便地从文档读取消息。

公开(公告)号：US20090050996A1

公开(公告)日：2009-02-26

申请号：US11987232

申请日：2007-11-28

申请人： Chien-Hung Liu ,  Sih-Dian Lee

发明人： Chien-Hung Liu ,  Sih-Dian Lee

IPC分类号： H01L31/0203 ,  H01L31/18 ,  H01L21/58 ,  H01L23/15

CPC分类号： H01L31/0203 ,  H01L23/3114 ,  H01L24/05 ,  H01L24/13 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14687 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/00

摘要： Electronic device wafer level scale packages and fabrication methods thereof. A semiconductor wafer with a plurality of electronic devices formed thereon is provided. The semiconductor wafer is bonded with a supporting substrate. The back of the semiconductor substrate is thinned. A first trench is formed by etching the semiconductor exposing an inter-layered dielectric layer. An insulating layer is conformably deposited on the back of the semiconductor substrate. The insulating layer on the bottom of the first trench is removed to create a second trench. The insulating layer and the ILD layer are sequentially removed exposing part of a pair of contact pads. A conductive layer is conformably formed on the back of the semiconductor. After the conductive layer is patterned, the conductive layer and the contact pads construct an S-shaped connection. Next, an exterior connection and terminal contact pads are subsequently formed.

摘要翻译： 电子装置晶圆级规包装及其制造方法。 提供了形成有多个电子器件的半导体晶片。 半导体晶片与支撑基板结合。 半导体衬底的背面变薄。 通过蚀刻暴露层间电介质层的半导体形成第一沟槽。 绝缘层顺应地沉积在半导体衬底的背面上。 去除第一沟槽底部的绝缘层以产生第二沟槽。 依次去除绝缘层和ILD层，暴露一对接触焊盘的一部分。 导电层顺应地形成在半导体的背面上。 导电层被图案化之后，导电层和接触垫构成S形连接。 接下来，随后形成外部连接和端子接触焊盘。

公开(公告)号：US20080182355A1

公开(公告)日：2008-07-31

申请号：US11657734

申请日：2007-01-25

申请人： Chien-Hung Liu

发明人： Chien-Hung Liu

IPC分类号： H01L21/00 ,  H01L31/0203

CPC分类号： H01L27/14618 ,  H01L24/16 ,  H01L25/042 ,  H01L27/14683 ,  H01L2224/0554 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A conducting layer in a chip package module includes one or a plurality of through hole penetrating the top of a base being disposed at the bottom of an insulating layer in the chip package module, and inner wall of the through hole being applied with insulation material so that the conductive layer subsequently constructed to the peripheral of the insulation layer may pass the through hole to extend to where above the base before construction of a masking layer and multiple circuit pins to complete construction of the conducting layer that is totally enveloped so to prevent easy oxidization at the conducting layer and improve stability of the chip package to avoid breaking up due to external force applied.

摘要翻译： 芯片封装模块中的导电层包括穿过基片顶部的一个或多个通孔，其设置在芯片封装模块中的绝缘层的底部，并且通孔的内壁被施加绝缘材料 随后构造到绝缘层的周边的导电层可以在构造掩模层和多个电路引脚之前通过通孔延伸到基底之上，以完成包封的导电层的构造，从而防止容易 导电层氧化，提高芯片封装的稳定性，避免施加外力而导致断裂。

公开(公告)号：US07299016B2

公开(公告)日：2007-11-20

申请号：US11329245

申请日：2006-01-11

申请人： Chien-Hung Liu

发明人： Chien-Hung Liu

IPC分类号： H01Q11/12

CPC分类号： G09G3/3406 ,  G09G2320/0606 ,  G09G2320/0626 ,  H04M1/22 ,  H04W52/027 ,  Y02D70/00

摘要： The present invention discloses a communication device with an adjustable brightness that includes a control circuit coupled to a modulating unit, and the modulating unit includes a tuning button disposed on the communication device that allows user to make adjustments or controls by the tuning button to produce a first set value, and the modulating unit converts the power received by a power supply circuit of the communication device into a corresponding operating voltage according to the first set value and sends the operating voltage to a light emitting unit of the communication device for projecting a light source according to the magnitude of the operating voltage, so as to adjust and change the brightness of the light emitting unit, and achieve the effects of saving power and extending the life of the light emitting units.

摘要翻译： 本发明公开了一种具有可调节亮度的通信设备，其包括耦合到调制单元的控制电路，并且调制单元包括设置在通信设备上的调谐按钮，其允许用户通过调谐按钮进行调节或控制以产生 第一设定值，并且调制单元根据第一设定值将由通信设备的电源电路接收的功率转换为相应的工作电压，并将工作电压发送到用于投射光的通信设备的发光单元 源，根据工作电压的大小，调整和改变发光单元的亮度，并实现节能和延长发光单元寿命的效果。

公开(公告)号：US20050142871A1

公开(公告)日：2005-06-30

申请号：US10819137

申请日：2004-04-07

申请人： Chien-Hung Liu ,  Ming-Huan Yang ,  Jane Chang ,  Chun-Jung Chen ,  Chao-Kai Cheng ,  Kou-Chen Liu

发明人： Chien-Hung Liu ,  Ming-Huan Yang ,  Jane Chang ,  Chun-Jung Chen ,  Chao-Kai Cheng ,  Kou-Chen Liu

IPC分类号： H01L21/20 ,  H01L21/288 ,  H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L29/417 ,  H01L29/45 ,  H05K3/00 ,  H05K3/32 ,  H05K3/40

CPC分类号： H01L29/66742 ,  H01L21/288 ,  H01L21/76802 ,  H01L21/76838 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66765 ,  H05K3/002 ,  H05K3/4069 ,  H05K2203/013 ,  H05K2203/0783

摘要： A method of forming a conductive via plug is disclosed. The conductive via plug is formed by printing a solution comprising a solvent with insulating material dissolve capability and a conductive material by an inkjet method. The formed conductive via plug has a low resistivity and thus may serve as an electrical connection between two separate conductive layers. This manufacturing method of the conductive via plug may achieve simultaneously deposition, patterning and etching purposes, which significantly simplifies the manufacturing process.

摘要翻译： 公开了形成导电通孔的方法。 导电通孔插塞是通过用喷墨法印刷包含具有绝缘材料溶剂的溶剂的溶液和导电材料而形成的。 所形成的导电通孔塞具有低电阻率，因此可以用作两个分开的导电层之间的电连接。 导电通孔插头的这种制造方法可以实现同时沉积，图案化和蚀刻目的，这显着简化了制造工艺。

公开(公告)号：US20050006694A1

公开(公告)日：2005-01-13

申请号：US10682861

申请日：2003-10-14

申请人： Chien-Hung Liu

发明人： Chien-Hung Liu

IPC分类号： H01L21/8246 ,  H01L27/115 ,  H01L29/792 ,  H01L29/788

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7923

摘要： A NAND type dual bit nitride read only memory and a method for fabricating thereof are provided. Firstly, a plurality of isolation layers, which are spaced and parallel to each other are formed in the substrate. Next, a plurality of word lines and a plurality of oxide-nitride-oxide (ONO) stack structures are formed on the substrate. The word lines are spaced and parallel to each other, and also the word lines are perpendicular to the isolation layers. Each of the ONO stack structure is located between the corresponding word line and the substrate. And then a plurality of discontinuous bit lines, which are located between the word lines and between the isolation layers are formed on the substrate. The structure of the present invention of the NAND type dual bit nitride read only memory is similar to that of a complementary metal-oxide semiconductor (CMOS), and their fabrication processes are fully compatible.

摘要翻译： 提供NAND型双位氮化物只读存储器及其制造方法。 首先，在衬底中形成彼此间隔开并平行的多个隔离层。 接下来，在基板上形成多个字线和多个氧化物 - 氮化物 - 氧化物（ONO）堆叠结构。 字线彼此间隔开并平行，字线也垂直于隔离层。 每个ONO堆叠结构位于相应的字线和基板之间。 然后，在基板上形成位于字线之间和隔离层之间的多个不连续位线。 本发明的NAND型双位氮化物只读存储器的结构类似于互补金属氧化物半导体（CMOS）的结构，并且它们的制造工艺是完全兼容的。

公开(公告)号：US06841830B2

公开(公告)日：2005-01-11

申请号：US10627637

申请日：2003-07-28

申请人： Chien-Hung Liu ,  Jian-Chiun Liou ,  Chun-Jung Chen ,  Je-Ping Hu

发明人： Chien-Hung Liu ,  Jian-Chiun Liou ,  Chun-Jung Chen ,  Je-Ping Hu

IPC分类号： B41J2/14 ,  H01L21/324 ,  H01L27/06 ,  H01L29/78 ,  H01L29/76 ,  G01R19/00

CPC分类号： H01L29/78 ,  B41J2/14129 ,  B41J2002/14387 ,  B41J2202/13 ,  H01L21/324 ,  H01L27/0629

摘要： A MOSFET and the method for fabricating them are disclosed to make the inkjet head chips. The MOSFET has the scaled-down junction formation for the source and drain. Using a lower temperature process and interlayer dielectric, the source and drain dopants can not be diffused deeply due to high-temperature driver-in. The contact holes of the drain are provided with plugs of refractory material to avoid spiking between the metal and silicon. This achieves the requirement of high-density devices on the print head chip.

摘要翻译： 公开了一种MOSFET及其制造方法，以制造喷墨头芯片。 MOSFET具有用于源极和漏极的按比例缩小的结形成。 使用较低温度工艺和层间电介质，源极和漏极掺杂物由于高温驱动而不能深入扩散。 漏斗的接触孔设置有耐火材料塞，以避免金属和硅之间的尖峰。 这实现了打印头芯片上高密度设备的要求。