公开(公告)号：US20120070979A1

公开(公告)日：2012-03-22

申请号：US12887737

申请日：2010-09-22

申请人： Felix P. Anderson ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

发明人： Felix P. Anderson ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

IPC分类号： H01L21/768 ,  C25D5/12 ,  C25D5/14 ,  H01L21/02

CPC分类号： H01L21/7684 ,  C25D3/38 ,  C25D5/10 ,  C25D5/12 ,  H01L21/2885 ,  H01L21/76877

摘要： The disclosure relates generally to semiconductor device fabrication, and more particularly to methods of electroplating used in semiconductor device fabrication. A method of electroplating includes: immersing an in-process substrate into an electrolytic plating solution to form a first metal layer on the in-process substrate; then performing a first chemical-mechanical polish to a liner on the in-process substrate followed by immersing the in-process substrate into the electrolytic plating solution to form a second metal layer on the first metal layer and the liner; and performing a second chemical-mechanical polish to the liner.

摘要翻译： 本公开一般涉及半导体器件制造，更具体地涉及用于半导体器件制造中的电镀方法。 电镀方法包括：将处理后的基板浸入电解镀液中以在工艺衬底上形成第一金属层; 然后对所述工艺衬底上的衬垫进行第一化学机械抛光，然后将所述工艺衬底浸入所述电解电镀溶液中，以在所述第一金属层和所述衬垫上形成第二金属层; 以及对所述衬垫执行第二化学机械抛光。

公开(公告)号：US20120042714A1

公开(公告)日：2012-02-23

申请号：US12858961

申请日：2010-08-18

申请人： Anthony K. Stamper

发明人： Anthony K. Stamper

IPC分类号： G01M3/04

CPC分类号： G01M3/045 ,  G01M3/047 ,  G01M3/186

摘要： A hermeticity sensor for a device includes a beam positioned within a substantially hermetically sealed cavity. The beam includes a stress that changes in response to being exposed to ambient from outside the cavity. A related method is also provided.

摘要翻译： 用于装置的气密传感器包括位于基本上密封的空腔内的梁。 梁包括响应于从外部暴露于环境的应力。 还提供了相关的方法。

公开(公告)号：US08053901B2

公开(公告)日：2011-11-08

申请号：US12917154

申请日：2010-11-01

申请人： Jeffrey P. Gambino ,  Anthony K. Stamper

发明人： Jeffrey P. Gambino ,  Anthony K. Stamper

IPC分类号： H01L23/48

CPC分类号： H01L21/02167 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/312 ,  H01L21/3121 ,  H01L21/3122 ,  H01L21/3148 ,  H01L21/31612 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The present invention provides a method of forming a rigid interconnect structure, and the device therefrom, including the steps of providing a lower metal wiring layer having first metal lines positioned within a lower low-k dielectric; depositing an upper low-k dielectric atop the lower metal wiring layer; etching at least one portion of the upper low-k dielectric to provide at least one via to the first metal lines; forming rigid dielectric sidewall spacers in at least one via of the upper low-k dielectric; and forming second metal lines in at least one portion of the upper low-k dielectric. The rigid dielectric sidewall spacers may comprise of SiCH, SiC, SiNH, SiN, or SiO2. Alternatively, the via region of the interconnect structure may be strengthened with a mechanically rigid dielectric comprising SiO2, SiCOH, or doped silicate glass.

摘要翻译： 本发明提供一种形成刚性互连结构及其装置的方法，包括以下步骤：提供具有位于下部低k电介质内的第一金属线的下金属布线层; 在下部金属布线层的顶部沉积上部低k电介质; 蚀刻上部低k电介质的至少一部分以向第一金属线提供至少一个通孔; 在所述上部低k电介质的至少一个通路中形成刚性电介质侧壁间隔物; 以及在所述上部低k电介质的至少一部分中形成第二金属线。 刚性电介质侧壁间隔物可以包括SiCH，SiC，SiNH，SiN或SiO 2。 或者，互连结构的通孔区域可以用包含SiO 2，SiCOH或掺杂的硅酸盐玻璃的机械刚性电介质来加强。

公开(公告)号：US20110201151A1

公开(公告)日：2011-08-18

申请号：US13038467

申请日：2011-03-02

申请人： Jeffrey P. Gambino ,  Anthony K. Stamper

发明人： Jeffrey P. Gambino ,  Anthony K. Stamper

IPC分类号： H01L21/60

CPC分类号： G06F17/5068 ,  H01L23/3672 ,  H01L23/473 ,  H01L23/481 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/12044

摘要： Bottom sides of two semiconductor substrates are brought together with at least one bonding material layer therebetween and bonded to form a bonded substrate. A cavity with two openings and a contiguous path therebetween is provided within the at least one bonding layer. At least one through substrate via and other metal interconnect structures are formed within the bonded substrate. The cavity is employed as a cooling channel through which a cooling fluid flows to cool the bonded semiconductor substrate during the operation of the semiconductor devices in the bonded substrate. Alternatively, a conductive cooling fin with two end portions and a contiguous path therebetween is formed within the at least one bonding layer. The two end portions of the conductive cooling fin are connected to heat sinks to cool the bonded semiconductor substrate during the operation of the semiconductor devices in the bonded substrate.

摘要翻译： 将两个半导体衬底的底侧与其间的至少一个接合材料层接合在一起，并结合以形成键合衬底。 在所述至少一个接合层内设置有具有两个开口的腔体和它们之间的连续路径。 在键合衬底内形成至少一个通过衬底通孔和其它金属互连结构。 在该键合衬底中的半导体器件的操作期间，使用该空腔作为冷却通道，通过该冷却通道冷却流体以冷却接合的半导体衬底。 或者，在至少一个接合层内形成具有两个端部的导电冷却翅片和它们之间的连续路径。 导电冷却翅片的两个端部连接到散热器，以在键合衬底中的半导体器件的操作期间冷却接合的半导体衬底。

公开(公告)号：US07968975B2

公开(公告)日：2011-06-28

申请号：US12188234

申请日：2008-08-08

申请人： David S. Collins ,  Alvin Joseph ,  Peter J. Lindgren ,  Anthony K. Stamper ,  Kimball M. Watson

发明人： David S. Collins ,  Alvin Joseph ,  Peter J. Lindgren ,  Anthony K. Stamper ,  Kimball M. Watson

IPC分类号： H01L29/40 ,  H01L21/44

CPC分类号： H01L23/522 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

摘要： An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.

摘要翻译： 通过半导体衬底和接触通过级介电层形成贯穿衬底通孔（TSV）的阵列。 直接在接触通路层电介质层上形成嵌入其中的金属线电介质层和线路级金属布线结构。 线级金属布线结构包括填充有金属线级介电层的隔离部分的奶酪孔。 在一个实施例中，整个烘干孔位于TSV阵列的区域的外部，以使TSV和线路级金属布线结构之间的接触面积达到最大。 在另一个实施例中，形成了覆盖TSV阵列中的整个接缝的一组干酪孔，以防止在电镀过程中在TSV的接缝中捕获任何电镀溶液，以防止接缝处的TSV的腐蚀。

公开(公告)号：US07915158B2

公开(公告)日：2011-03-29

申请号：US12144071

申请日：2008-06-23

申请人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

发明人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/3148 ,  H01L21/318 ,  H01L21/3185 ,  H01L27/0248

摘要： A method for forming an on-chip high frequency electro-static discharge device is described. In one embodiment, a wafer with a multi-metal level wiring is provided. The wafer includes a first dielectric layer with more than one electrode formed therein, a second dielectric layer disposed over the first dielectric layer with more than one electrode formed therein and more than one via connecting the more than one electrode in the first dielectric layer to a respective more than one electrode in the second dielectric layer. The more than one via is misaligned a predetermined amount with the more than one electrodes in the first dielectric layer and the second dielectric layer. The at least one of the misaligned vias forms a narrow gap with another misaligned via. A cavity trench is formed through the second dielectric layer between the narrow gap that separates the misaligned vias.

摘要翻译： 描述形成片上高频静电放电装置的方法。 在一个实施例中，提供具有多金属层布线的晶片。 该晶片包括：第一电介质层，其中形成有多于一个电极;第二电介质层，设置在第一电介质层上，其中形成有多于一个电极，多个通孔将第一介电层中的多于一个的电极连接到 在第二介电层中分别有一个以上的电极。 多于一个通孔与第一介电层和第二介电层中的多于一个的电极不对准预定量。 至少一个不对齐的通孔与另一个不对齐的通孔形成了狭窄的间隙。 在分隔未对准的通孔的窄间隙之间通过第二介电层形成腔沟槽。

公开(公告)号：US20100320571A1

公开(公告)日：2010-12-23

申请号：US12488899

申请日：2009-06-22

申请人： John J. Benoit ,  Mattias E. Dahlstrom ,  Mark D. Dupuis ,  Peter B. Gray ,  Anthony K. Stamper

发明人： John J. Benoit ,  Mattias E. Dahlstrom ,  Mark D. Dupuis ,  Peter B. Gray ,  Anthony K. Stamper

IPC分类号： H01L29/73 ,  H01L21/331

CPC分类号： H01L29/732 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/167 ,  H01L29/207 ,  H01L29/227 ,  H01L29/34 ,  H01L29/66272

摘要： A bipolar transistor structure and a method for fabricating the bipolar transistor structure include: (1) a collector structure located at least in-part within a semiconductor substrate; (2) a base structure contacting the collector structure; and (3) an emitter structure contacting the base structure. The interface of the emitter structure and the base structure includes an oxygen impurity and at least one impurity selected from the group consisting of a fluorine impurity and a carbon impurity, to enhance performance of a bipolar transistor within the bipolar transistor structure. The impurities may be introduced into the interface by plasma etch treatment, or alternatively a thermal treatment followed by an anhydrous ammonia and hydrogen fluoride treatment, of a base material from which is comprised the base structure.

摘要翻译： 双极晶体管结构和制造双极晶体管结构的方法包括：（1）至少部分地位于半导体衬底内的集电极结构; （2）与收集器结构接触的基部结构; 和（3）与基底结构接触的发射体结构。 发射极结构和基极结构的界面包括氧杂质和选自氟杂质和碳杂质的至少一种杂质，以增强双极晶体管结构内的双极晶体管的性能。 杂质可以通过等离子体蚀刻处理或者替代地进行无水氨和氟化氢处理的热处理而引入到界面中，其中基体材料由基底结构组成。

公开(公告)号：US07772028B2

公开(公告)日：2010-08-10

申请号：US11959841

申请日：2007-12-19

申请人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel ,  Anthony K. Stamper

发明人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel ,  Anthony K. Stamper

IPC分类号： H01L21/66

CPC分类号： H01L27/14636 ,  H01L21/76819 ,  H01L21/76834 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14683

摘要： A CMOS image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The CMOS image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.

摘要翻译： CMOS图像传感器和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合较薄的层间电介质堆叠以产生呈现增加的光灵敏度的像素阵列。 CMOS图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属的最小厚度的结构，或者具有从每个像素的光路中选择性地去除的阻挡层金属的部分，从而使反射率最小化的结构。 也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。 在另一个实施例中，阻挡金属层可以通过自对准沉积形成在Cu金属化之上。

公开(公告)号：US07674705B2

公开(公告)日：2010-03-09

申请号：US12201266

申请日：2008-08-29

申请人： Anthony K. Stamper

发明人： Anthony K. Stamper

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/31116 ,  H01L21/76807 ,  H01L28/87

摘要： A method of forming a semiconductor device. A first wiring level is formed on a top surface of a substrate. The first wiring level includes alternating layers of a first dielectric material and a second dielectric material. The layers of the first dielectric material includes at least two layers of the first dielectric material. The layers of the second dielectric material includes at least two layers of the second dielectric material. The first dielectric material includes an organic dielectric material. The second dielectric material includes an inorganic dielectric material. The substrate includes one or more dielectric materials. A first layer of the layers of the first dielectric material includes the organic dielectric material being in direct mechanical contact with the substrate. The layers of the first dielectric material and the layers of the second dielectric material are a same number of layers.

摘要翻译： 一种形成半导体器件的方法。 在基板的顶表面上形成第一布线层。 第一布线层包括第一介电材料和第二介电材料的交替层。 第一介电材料的层包括至少两层第一介电材料。 第二电介质材料的层包括至少两层第二电介质材料。 第一电介质材料包括有机介电材料。 第二电介质材料包括无机介电材料。 衬底包括一种或多种介电材料。 第一介电材料层的第一层包括与衬底直接机械接触的有机介电材料。 第一介电材料的层和第二介电材料的层是相同数量的层。

公开(公告)号：US07669170B2

公开(公告)日：2010-02-23

申请号：US11676185

申请日：2007-02-16

申请人： John M. Cohn ,  Jason Hibbeler ,  Anthony K. Stamper ,  Jed H. Rankin

发明人： John M. Cohn ,  Jason Hibbeler ,  Anthony K. Stamper ,  Jed H. Rankin

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A circuit layout methology is provided for eliminating the extra processing time and file-space requirements associated with the optical proximity correction (OPC) of a VLSI design. The methodology starts with the design rules for a given manufacturing technology and establishes a new set of layer-specific grid values. A layout obeying these new grid requirements leads to a significant reduction in data preparation time, cost, and file size. A layout-migration tool can be used to modify an existing layout in order to enforce the new grid requirements.

摘要翻译： 提供电路布局方案，用于消除与VLSI设计的光学邻近校正（OPC）相关联的额外处理时间和文件空间要求。 该方法从给定制造技术的设计规则开始，并建立一组新的层特定网格值。 符合这些新网格要求的布局导致数据准备时间，成本和文件大小显着降低。 布局迁移工具可用于修改现有布局，以实施新的网格要求。