公开(公告)号：US20140246698A1

公开(公告)日：2014-09-04

申请号：US13783517

申请日：2013-03-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stefan Flachowsky ,  Ralf Richter ,  Jan Hoentschel

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823418 ,  H01L21/28518 ,  H01L21/823412 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/66431 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: When forming sophisticated P-channel transistors, a semiconductor alloy layer is formed on the surface of the semiconductor layer including the transistor active region. When a metal silicide layer is formed contiguous to this semiconductor alloy layer, an agglomeration of the metal silicide layer into isolated clusters is observed. In order to solve this problem, the present invention proposes a method and a semiconductor device wherein the portion of the semiconductor alloy layer lying on the source and drain regions of the transistor is removed before formation of the metal silicide layer is performed. In this manner, the metal silicide layer is formed so as to be contiguous to the semiconductor layer, and not to the semiconductor alloy layer.

Abstract translation: 当形成复杂的P沟道晶体管时，在包括晶体管有源区的半导体层的表面上形成半导体合金层。 当与该半导体合金层邻接形成金属硅化物层时，观察到金属硅化物层与分离的团簇的聚集。 为了解决这个问题，本发明提出一种方法和半导体器件，其中在形成金属硅化物层之前去除位于晶体管的源极和漏极区域上的半导体合金层的部分。 以这种方式，金属硅化物层形成为与半导体层邻接，而不形成为半导体合金层。

公开(公告)号：US20140197498A1

公开(公告)日：2014-07-17

申请号：US13740974

申请日：2013-01-14

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Nicolas Sasiat ,  Ran Yan

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/665 ,  H01L21/823443 ,  H01L21/823468 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming over a semiconductor substrate a gate structure. The method further includes depositing a non-conformal spacer material around the gate structure. A protection mask is formed over the non-conformal spacer material. The method etches the non-conformal spacer material and protection mask to form a salicidation spacer. Further, a self-aligned silicide contact is formed adjacent the salicidation spacer.

Abstract translation: 本文提供用于制造集成电路的集成电路和方法。 在一个实施例中，制造集成电路的方法包括在半导体衬底上形成栅极结构。 该方法还包括在栅极结构周围沉积非共形间隔物材料。 在非保形间隔物材料上形成保护罩。 该方法蚀刻非共形间隔物材料和保护掩模以形成防腐隔离物。 此外，邻近该盐化隔离层形成自对准的硅化物接触。

公开(公告)号：US20130306967A1

公开(公告)日：2013-11-21

申请号：US13869162

申请日：2013-04-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Robert Mulfinger ,  Vassilios Papageorgiou

IPC: H01L23/58

CPC classification number: H01L23/58 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a sophisticated semiconductor device, FINFET elements may be provided with individually accessible semiconductor fins which may be connected to a controllable interconnect structure for appropriately adjusting the transistor configuration, for instance with respect to current drive capability, replacing defective semiconductor fins and the like. Consequently, different transistor configurations may be obtained on the basis of a standard transistor cell architecture, which may result in increased production yield of highly complex manufacturing strategies in forming non-planar transistor devices.

Abstract translation: 在复杂的半导体器件中，FINFET元件可以设置有单独可访问的半导体鳍片，其可以连接到可控制的互连结构，以适当地调整晶体管配置，例如关于电流驱动能力，替换有缺陷的半导体鳍片等。 因此，可以在标准晶体管单元架构的基础上获得不同的晶体管配置，这可能导致在形成非平面晶体管器件时高度复杂的制造策略的生产成本增加。

公开(公告)号：US09881841B2

公开(公告)日：2018-01-30

申请号：US15074483

申请日：2016-03-18

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Alban Zaka ,  Ran Yan ,  El Mehdi Bazizi ,  Jan Hoentschel

IPC: H01L21/336 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/266 ,  H01L21/324 ,  H01L29/66 ,  H01L29/167 ,  H01L21/268 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/10

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/268 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L27/0924 ,  H01L29/1041 ,  H01L29/167 ,  H01L29/66492 ,  H01L29/6656 ,  H01L29/6659

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure having an n-channel gate stack and a p-channel gate stack formed over a semiconductor substrate. The method includes forming halo implant regions in the semiconductor substrate adjacent the p-channel gate stack and forming extension implant regions in the semiconductor substrate adjacent the p-channel gate stack. The method further includes annealing the halo implant regions and the extension implant regions in the semiconductor substrate adjacent the p-channel gate stack. Also, the method forms extension implant regions in the semiconductor substrate adjacent the n-channel gate stack.

公开(公告)号：US09608112B2

公开(公告)日：2017-03-28

申请号：US14816337

申请日：2015-08-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Sven Beyer ,  Tom Hasche ,  Jan Hoentschel

IPC: H01L27/01 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L27/06 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/66537 ,  H01L21/743 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/7838 ,  H01L29/7843

Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a method of forming a semiconductor device, the method including providing an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material, forming a gate structure on the active semiconductor layer in an active region of the SOI substrate, partially exposing the base substrate for forming at least one bulk exposed region after the gate structure is formed, and forming a contact structure for contacting the at least one bulk exposed region.

公开(公告)号：US09553046B2

公开(公告)日：2017-01-24

申请号：US14718502

申请日：2015-05-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Peter Baars ,  Hans-Peter Moll

IPC: H01L21/331 ,  H01L23/525 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L23/5256 ,  H01L21/84 ,  H01L27/1203

Abstract: A method of forming a semiconductor device comprising a fuse is provided including providing a semiconductor-on-insulator (SOI) structure comprising an insulating layer and a semiconductor layer formed on the insulating layer, forming raised semiconductor regions on the semiconductor layer adjacent to a central portion of the semiconductor layer and performing a silicidation process of the central portion of the semiconductor layer and the raised semiconductor regions to form a silicided semiconductor layer and silicided raised semiconductor regions.

Abstract translation: 提供一种形成包括熔丝的半导体器件的方法，包括：提供绝缘层上的绝缘体上半导体结构（SOI）结构和形成在绝缘层上的半导体层，在与中心相邻的半导体层上形成凸起的半导体区域 并且对半导体层的中心部分和凸起的半导体区域进行硅化处理，以形成硅化半导体层和硅化凸起的半导体区域。

公开(公告)号：US09502564B2

公开(公告)日：2016-11-22

申请号：US15164374

申请日：2016-05-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars ,  Jan Hoentschel

IPC: H01L29/10 ,  H01L29/76 ,  H01L31/036 ,  H01L31/112 ,  H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7838 ,  H01L29/7849 ,  H01L29/78603 ,  H01L29/78639 ,  H01L29/78654

Abstract: A semiconductor device includes an active region formed in a semiconductor substrate, a gate structure disposed over the active region, source/drain regions formed in the active region in alignment with the gate structure, and a buried insulating material region disposed in the active region under the gate structure. The buried insulating material region is surrounded by the active region and borders a channel region in the active region below the gate structure along a depth of the active region. The source/drain regions have a depth greater than a top surface of the buried insulating material region.

Abstract translation: 半导体器件包括形成在半导体衬底中的有源区，设置在有源区上的栅极结构，形成在与栅结构对准的有源区中的源极/漏极区，以及设置在有源区内的掩埋绝缘材料区 门结构。 掩埋绝缘材料区域被有源区域包围，并且沿着有源区域的深度与栅极结构下方的有源区域中的沟道区域相邻。 源/漏区具有大于掩埋绝缘材料区的顶表面的深度。

公开(公告)号：US20160315162A1

公开(公告)日：2016-10-27

申请号：US15201838

申请日：2016-07-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Peter Javorka ,  Jan Hoentschel ,  Stefan Flachowsky

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L29/42376 ,  H01L21/28008 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/28123 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66575 ,  H01L29/78

Abstract: A semiconductor device structure includes an active region positioned in a semiconductor substrate and a gate structure of a transistor positioned above the active region. The gate structure includes a gate insulating layer, a gate metal layer positioned above the gate insulating layer and a trimmed gate electrode material layer positioned above the gate metal layer. A length of at least a portion of the trimmed gate electrode material layer in a gate length direction of the transistor is less than a length of at least the gate metal layer in the gate length direction.

Abstract translation: 半导体器件结构包括位于半导体衬底中的有源区和位于有源区上方的晶体管的栅极结构。 栅极结构包括栅极绝缘层，位于栅极绝缘层上方的栅极金属层和位于栅极金属层上方的修整的栅电极材料层。 在晶体管的栅极长度方向上的修整的栅电极材料层的至少一部分的长度小于栅极金属层在栅极长度方向上的长度。

公开(公告)号：US20160300947A1

公开(公告)日：2016-10-13

申请号：US14680172

申请日：2015-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Alban Zaka ,  Jan Hoentschel

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L21/823814 ,  H01L21/823418 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78639 ,  H01L29/78654

Abstract: The present disclosure provides, in a first aspect, a semiconductor device including an SOI substrate portion, a gate structure formed on the SOI substrate portion and source and drain regions having respective source and drain height levels, wherein the source and drain height levels are different. The semiconductor device may be formed by forming a gate structure over an SOI substrate portion, recessing the SOI substrate portion at one side of the gate structure so as to form a trench adjacent to the gate structure and forming source and drain regions at opposing sides of the gate structure, one of the source and drain regions being formed in the trench.

Abstract translation: 本公开在第一方面提供了一种半导体器件，其包括SOI衬底部分，形成在SOI衬底部分上的栅极结构以及具有各自的源极和漏极高度水平的源极和漏极区域，其中源极和漏极高度水平是不同的 。 可以通过在SOI衬底部分上形成栅极结构来形成半导体器件，在栅极结构的一侧凹入SOI衬底部分，以形成与栅极结构相邻的沟槽，并在栅极结构的相对侧形成源极和漏极区域 栅极结构，其中一个源极和漏极区域形成在沟槽中。

公开(公告)号：US09449972B1

公开(公告)日：2016-09-20

申请号：US14640151

申请日：2015-03-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Illgen ,  Jan Hoentschel

IPC: H01L29/51 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/28 ,  H01L27/088 ,  H01L29/423 ,  H01L27/11 ,  H01L21/311 ,  H01L21/3065

CPC classification number: H01L27/0886 ,  H01L21/28291 ,  H01L21/823431 ,  H01L21/823462 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/516 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66553 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7851

Abstract: The present disclosure provides, in a first aspect, a semiconductor device, including a semiconductor substrate and a gate structure formed over the semiconductor substrate, wherein the gate structure comprises a fin and a ferroelectric high-k material formed at least over sidewall surfaces of the fin. Herein, a first thickness defined by a thickness of the ferroelectric high-k material formed over sidewalls of the fin is substantially greater than a second thickness defined by a thickness of the ferroelectric high-k material formed over an upper surface of the fin.

Abstract translation: 本公开在第一方面提供一种半导体器件，其包括形成在半导体衬底上的半导体衬底和栅极结构，其中栅极结构包括鳍状物和至少形成在所述半导体衬底的侧壁表面上的铁电高k材料 鳍。 这里，由在翅片的侧壁上形成的铁电高k材料的厚度限定的第一厚度基本上大于由在翅片的上表面上形成的铁电高k材料的厚度限定的第二厚度。