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81.发明授权Data protection method for a semiconductor memory and corresponding protected memory device 失效半导体存储器和相应的受保护存储器件的数据保护方法公开(公告)号：US06286086B1
公开(公告)日：2001-09-04
申请号：US09220127
申请日：1998-12-23
IPC分类号： G06F1214
CPC分类号： G07F7/1008 , G06F12/1433 , G06F21/79 , G06Q20/341 , G06Q20/357 , G11C8/20 , G11C16/22
摘要： A method of protecting data in a semiconductor electronic memory, which includes using a protected memory portion within the matrix and respective dedicated decoding portions for storing, into the protected portion, a protection code without the address area of the matrix. The protection code can only be written and/or read through a command interpreter.
摘要翻译： 一种保护半导体电子存储器中的数据的方法，其包括在矩阵内使用受保护的存储器部分和各个专用解码部分，用于将保护代码存储在保护部分中，而没有矩阵的地址区域。 保护代码只能通过命令解释器进行写入和/或读取。
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82.发明授权公开(公告)号：US06266222B1
公开(公告)日：2001-07-24
申请号：US09223621
申请日：1998-12-30
IPC分类号： H02H904
CPC分类号： H01L27/0259 , H01L27/0251
摘要： An ESD protection network protects a CMOS circuit structure integrated in a semiconductor substrate. The circuit structure includes discrete circuit blocks formed in respective substrate portions which are electrically isolated from one another and independently powered from at least one primary voltage supply having a respective primary ground, and from at least one secondary voltage supply having a respective secondary ground. This network includes a first ESD protection element for an input stage of the circuit structure; a second ESD protection element for an output stage of the circuit structure, the first and second protection elements having an input/output pad of the integrated circuit structure in common; a first ESD protection element between the primary supply and the primary ground; and a second ESD protection element between the secondary supply and the secondary ground.
摘要翻译： ESD保护网络保护集成在半导体衬底中的CMOS电路结构。 电路结构包括形成在相应的衬底部分中的分立电路块，它们彼此电绝缘并且由至少一个具有各自的初级接地的初级电压源以及至少一个具有相应次级接地的次级电压源独立供电。 该网络包括用于电路结构的输入级的第一ESD保护元件; 用于所述电路结构的输出级的第二ESD保护元件，所述第一和第二保护元件具有所述集成电路结构的输入/输出焊盘; 主要供电和主地面之间的第一个ESD保护元件; 以及在次级电源和次级接地之间的第二ESD保护元件。
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公开(公告)号：US06184741B2
公开(公告)日：2001-02-06
申请号：US08900165
申请日：1997-07-28
IPC分类号： G05F110
CPC分类号： G11C5/145
摘要： A charge pump comprises at least one charge pump stage including a first diode having an anode and a cathode, and a capacitor having a first plate connected to the cathode of the diode and a second plate connected to a clock signal that periodically varies between a reference voltage and a supply voltage, the anode of said diode forming a first terminal of the charge pump. The charge pump further comprises a second diode having an anode connected to the cathode of the first diode and a cathode forming a second terminal of the charge pump, first switching means for selectively coupling the first terminal of the charge pump to the voltage supply and second switching means for selectively coupling the second terminal of the charge pump to the reference voltage. The first switching means and the second switching means are respectively closed and open in a first operating condition whereby the second terminal of the charge pump acquires a voltage of the same polarity but higher in absolute value than said supply voltage. The first switching means and the second switching means are respectively open and closed in a second operating condition whereby the first terminal of the charge pump acquires a voltage of opposite polarity with respect to said voltage supply.
摘要翻译： 电荷泵包括至少一个电荷泵级，其包括具有阳极和阴极的第一二极管，以及具有连接到二极管的阴极的第一板的电容器和连接到时钟信号的第二板，所述时钟信号周期性地在参考 电压和电源电压，所述二极管的阳极形成电荷泵的第一端子。 电荷泵还包括具有连接到第一二极管的阴极的阳极和形成电荷泵的第二端子的阴极的第二二极管，用于选择性地将电荷泵的第一端子耦合到电压源的第一开关装置和第二二极管 用于选择性地将电荷泵的第二端子耦合到参考电压的开关装置。 第一开关装置和第二开关装置分别在第一操作条件下闭合和断开，由此电荷泵的第二端子获得与所述电源电压相同的极性但绝对值高的电压。 第一开关装置和第二开关装置分别在第二操作条件下打开和关闭，由此电荷泵的第一端子获得相对于所述电压源的极性相反的电压。
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公开(公告)号：US6151251A
公开(公告)日：2000-11-21
申请号：US295667
申请日：1999-04-21
IPC分类号： G05F3/20 , H01L27/115 , G11C11/34
CPC分类号： H01L27/115 , G05F3/205
摘要： A biasing device for biasing a memory cell having a substrate bias terminal associated therewith. The biasing device includes a first sub-threshold circuitry block adapted to supply an appropriate current during the device standby phase through a restore transistor connected between a supply voltage reference and the substrate bias terminal of the memory cell, and having a control terminal connected to a bias circuit, in turn connected between the supply voltage reference and a ground voltage reference to drive the restore transistor with a current of limited value. The device further includes a second feedback block for fast charging the substrate bias terminal, being connected between the supply voltage reference and the ground voltage reference and comprising a first bias transistor having a control terminal connected to the ground voltage reference via a stabilization transistor, having in turn a control terminal connected to an output node, and to the control terminal of a first regulation transistor connected between the supply voltage reference and the ground voltage reference, the stabilization transistor and first regulation transistor providing feedback for the bias transistor, thereby to restrict the voltage range of the output node.
摘要翻译： 一种用于偏置具有与其相关联的衬底偏置端子的存储单元的偏置装置。 偏置装置包括第一子阈值电路块，其适于在器件待机阶段期间通过连接在电源电压基准和存储单元的衬底偏置端之间的恢复晶体管提供适当的电流，并且具有连接到存储器单元的控制端 偏置电路又连接在电源参考电压和地电压基准之间，以有限的电流驱动恢复晶体管。 该装置还包括用于对衬底偏置端子进行快速充电的第二反馈块，其连接在电源电压基准和接地电压基准之间，并且包括具有经由稳定晶体管连接到接地电压基准的控制端的第一偏置晶体管， 连接到输出节点的控制终端，以及连接在电源电压基准和接地电压基准之间的第一调节晶体管的控制端，稳压晶体管和第一调节晶体管为偏置晶体管提供反馈，从而限制 输出节点的电压范围。
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公开(公告)号：US06060753A
公开(公告)日：2000-05-09
申请号：US889653
申请日：1997-07-08
IPC分类号： H01L27/092 , H01L29/76
CPC分类号： H01L27/0928
摘要： A low-noise output stage for an electronic circuit integrated on a semiconductor substrate is disclosed. The low-noise output stage comprises a complementary CMOS transistor pair including a P-channel pull-up transistor and an N-channel pull-down transistor, connected across a first terminal of the electronic circuit to receive a supply voltage, and a second terminal of the electronic circuit to receive a second reference potential. The transistors are connected together to form an output terminal of the electronic circuit for connection to an external load. The pull-down transistor is formed in a three-well structure to prevent propagation of a discharge current from the external load through the semiconductor substrate.
摘要翻译： 公开了一种用于集成在半导体衬底上的电子电路的低噪声输出级。 低噪声输出级包括互连CMOS晶体管对，其包括连接在电子电路的第一端子上以接收电源电压的P沟道上拉晶体管和N沟道下拉晶体管，以及第二端子 以接收第二参考电位。 晶体管连接在一起以形成用于连接到外部负载的电子电路的输出端子。 下拉晶体管形成为三阱结构，以防止放电电流从外部负载通过半导体衬底传播。
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公开(公告)号：US5982666A
公开(公告)日：1999-11-09
申请号：US13141
申请日：1998-01-26
申请人： Giovanni Campardo
发明人： Giovanni Campardo
CPC分类号： G11C16/28
摘要： A sense amplifier circuit for a semiconductor memory device comprises first current/voltage conversion means for converting a current of a memory cell to be read into a voltage signal, second current voltage/conversion means for converting a reference current into a reference voltage signal, and voltage comparator means for comparing the voltage signal with the reference voltage signal. The sense amplifier circuit comprises capacitive decoupling means for decoupling the voltage signal from the comparator means, and means for providing the capacitive decoupling means with an electric charge suitable for compensating an offset voltage introduced in the voltage signal by an offset current superimposed on the current of the memory cell to be read.
摘要翻译： 一种用于半导体存储器件的读出放大器电路包括用于将要读取的存储单元的电流转换为电压信号的第一电流/电压转换装置，用于将参考电流转换为参考电压信号的第二电流电压/转换装置，以及 电压比较器装置，用于将电压信号与参考电压信号进行比较。 感测放大器电路包括用于使来自比较器装置的电压信号去耦的电容去耦装置，以及用于向电容去耦装置提供适合于补偿在电压信号中引入的偏移电压的电荷的装置， 要读取的存储单元。
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87.发明授权
公开(公告)号：US5682349A
公开(公告)日：1997-10-28
申请号：US454650
申请日：1995-05-31
IPC分类号： G11C17/00 , G11C16/06 , G11C16/34 , G11C29/00 , G11C29/04 , G11C29/12 , G11C29/50 , H01L27/00 , G11C11/34
CPC分类号： G11C29/82 , G11C16/34 , G11C29/50 , G06F2201/81 , G11C16/04 , G11C2029/5006
摘要： Since fault phenomena such as lowering of the cell gain and cell emptying occur during normal operation the present invention proposes that in the memory device the row and/or column address decoding means (RDEC,CDEC) comprise at least one non-volatile memory (NVM) for address mapping and that the reading and writing control logic (CL) comprise means (TST) designed to identify cell faults, such as low grain, in the rows and/or columns of the matrix (MAT) of the memory device and writing means (WM) designed to write on said non-volatile memory (NVM) during normal operation addresses corresponding to redundant rows and/or columns (RID) present in the matrix (MAT) to rectify said faults.
摘要翻译： 由于在正常操作期间发生诸如电池增益和电池排空的降低的故障现象，本发明提出在存储器件中，行和/或列地址解码装置（RDEC，CDEC）包括至少一个非易失性存储器（NVM ），并且读写控制逻辑（CL）包括被设计用于识别存储器件的矩阵（MAT）的行和/或列中的单元故障（例如低纹理）的装置（TST），并且写入 用于在与存在于矩阵（MAT）中的冗余行和/或列（RID）对应的正常操作地址期间在所述非易失性存储器（NVM）上写入的装置（WM），以纠正所述故障。
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公开(公告)号：US5535157A
公开(公告)日：1996-07-09
申请号：US347653
申请日：1994-11-30
CPC分类号： G11C16/0416 , G11C16/04 , G11C16/16 , G11C16/22
摘要： An integrated device with electrically programmable and erasable memory cells, including one time programmable (OTP) read-only memory cells. A matrix of user memory cells is added at least one row of OTP cells sharing the column selection lines with the other cells. Similarly to the other cells, these have a selection terminal connected to a row selection line. The source terminals of such OTP cells in the row are connected to the device ground through a common selection transistor which is driven from the same row selection line.
摘要翻译： 具有电可编程和可擦除存储单元的集成器件，包括一次可编程（OTP）只读存储器单元。 将用户存储单元的矩阵添加到与其他单元共享列选择行的至少一行OTP单元。 与其他单元类似，它们具有连接到行选择线的选择端子。 该行中的这种OTP单元的源极端子通过从相同行选择线驱动的公共选择晶体管连接到器件地。
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公开(公告)号：US08759215B2
公开(公告)日：2014-06-24
申请号：US12537075
申请日：2009-08-06
IPC分类号： H01L21/44
CPC分类号： H01L24/06 , H01L21/76898 , H01L23/3121 , H01L23/49811 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/05552 , H01L2224/0557 , H01L2224/10126 , H01L2224/13009 , H01L2224/131 , H01L2224/13111 , H01L2224/13186 , H01L2224/16 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01014 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01072 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/04941 , H01L2224/13099 , H01L2924/00
摘要： A method for manufacturing solder bumps for through vias in a substrate having a first surface and a second surface opposed to each other. The method includes the steps of forming a blind hole extending in the substrate from the first surface for each via and filling each blind hole with a conductive filler; a deepest part of each filler includes a bump portion made of a solder material. The method further includes the step of removing a part of the substrate extending from the second surface to have at least the bump portions protrude from the substrate. The non-protruding part of each filler defines the corresponding via and the bump portion defines the corresponding bump.
摘要翻译： 一种用于制造具有彼此相对的第一表面和第二表面的基板中的通孔的焊料凸块的方法。 该方法包括以下步骤：从每个通孔的第一表面形成在基板中延伸的盲孔，并用导电填料填充每个盲孔; 每个填料的最深部分包括由焊料材料制成的凸起部分。 所述方法还包括从所述第二表面移除所述基板的一部分以至少具有从所述基板突出的凸起部的步骤。 每个填料的非突出部分限定相应的通孔，凸起部分限定相应的凸块。
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90.发明授权Error correcting codes for increased storage capacity in multilevel memory devices 有权错误纠正代码以增加多级存储器件的存储容量公开(公告)号：US08370702B2
公开(公告)日：2013-02-05
申请号：US12482400
申请日：2009-06-10
申请人： Paolo Amato , Giovanni Campardo
发明人： Paolo Amato , Giovanni Campardo
IPC分类号： H03M13/00
CPC分类号： H03M13/05 , G11C2029/0411 , H03M13/15 , H03M13/152 , H03M13/256 , H03M13/27 , H03M13/29 , H03M13/2933 , H03M13/2936 , H03M13/41
摘要： Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, data may be programmed and/or read from a matrix of nonvolatile memory cells with concatenated encoding/decoding schemes. In some embodiments, a calculation module may determine an actual bit per cell value of a given combination of parameters of a nonvolatile memory device. Still other embodiments may be described and claimed.
摘要翻译： 本公开的实施例提供了与具有纠错的多级编码相关的方法，系统和装置。 在一些实施例中，可以使用级联的编码/解码方案从非易失性存储器单元的矩阵中编程和/或读取数据。 在一些实施例中，计算模块可以确定非易失性存储器件的给定参数组合的每个单元值的实际位数。 可以描述和要求保护其他实施例。
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