公开(公告)号：US09548386B1

公开(公告)日：2017-01-17

申请号：US14840960

申请日：2015-08-31

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L29/78 ,  H01L21/32 ,  H01L21/02 ,  H01L21/308 ,  H01L21/324 ,  H01L21/306 ,  H01L21/311 ,  H01L21/283 ,  H01L29/165 ,  H01L29/10 ,  H01L29/66 ,  H01L27/12

CPC classification number: H01L27/1211 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/18 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/31116 ,  H01L21/32 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7845 ,  H01L29/785

Abstract: A method of forming a semiconductor structure that includes a tensily strained silicon fin extending upwards from a first portion of a substrate and in an nFET device region, and a SiGe fin structure extending upwards from a second portion of the substrate and in a pFET device region. In accordance with the present application, the SiGe fin structure comprises, from bottom to top, a lower SiGe fin that is relaxed and an upper SiGe fin, wherein the upper SiGe fin is compressively strained and has a germanium content that is greater than a germanium content of the lower SiGe fin.

Abstract translation: 一种形成半导体结构的方法，该半导体结构包括从衬底的第一部分和nFET器件区域向上延伸的紧张应变的硅鳍，以及从衬底的第二部分向上延伸的SiGe鳍结构以及pFET器件区域 。 根据本申请，SiGe鳍结构从底部到顶部包括松弛的下部SiGe鳍和上部SiGe鳍，其中上部SiGe鳍被压缩应变并且具有大于锗的锗含量 含量较低的SiGe鳍。

公开(公告)号：US09548213B2

公开(公告)日：2017-01-17

申请号：US14189294

申请日：2014-02-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Darsen D. Lu ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L29/66 ,  H01L21/311 ,  H01L29/78 ,  H01L21/308

CPC classification number: H01L29/7846 ,  H01L21/02236 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/31051 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a fin structure that includes forming a plurality of fin structures from a bulk semiconductor substrate and forming a dielectric spacer on a sidewall of each fin structure in the plurality of fin structure. A semiconductor spacer is formed on a sidewall of the dielectric spacer. A dielectric fill is formed in the space between the adjacent fin structures. The semiconductor spacer and a portion of the fin structures that is present below a lower surface of the dielectric spacer are oxidized. Oxidizing a base portion of the fin structures produces a first strain and oxidizing the semiconductor spacer produces a second strain that is opposite the first strain.

Abstract translation: 一种形成翅片结构的方法，其包括从体半导体衬底形成多个翅片结构，并在所述多个翅片结构中的每个翅片结构的侧壁上形成电介质间隔物。 在电介质间隔物的侧壁上形成半导体衬垫。 在相邻翅片结构之间的空间中形成介电填料。 存在于电介质隔板的下表面下方的半导体间隔物和翅片结构的一部分被氧化。 氧化翅片结构的基部产生第一应变并且氧化半导体间隔物产生与第一应变相反的第二应变。

公开(公告)号：US09431306B2

公开(公告)日：2016-08-30

申请号：US15075437

申请日：2016-03-21

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Bruce Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L21/02 ,  H01L21/84 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L21/3105

CPC classification number: H01L21/845 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a plurality of trenches to define a fin, forming a first layer of insulating material in the trenches, forming a sidewall spacer on opposite sides of the fin above an upper surface of the first layer, removing the first layer and performing a fin-trimming etching process to define a plurality of increased-size trenches. The method also includes forming a first oxidation-blocking layer of insulating material in the increased-size trenches, forming a second layer of insulating material above the oxidation-blocking layer, and performing a thermal anneal process to convert at least a part of the portion of the fin that is in contact with the second layer of insulating material into an oxide fin isolation region.

Abstract translation: 一种方法包括形成多个沟槽以限定翅片，在沟槽中形成绝缘材料的第一层，在第一层的上表面上方的翅片的相对侧上形成侧壁隔离物，去除第一层并执行 翅片修剪蚀刻工艺以限定多个增大尺寸的沟槽。 该方法还包括在增大尺寸的沟槽中形成绝缘材料的第一氧化阻挡层，在氧化阻挡层上方形成第二层绝缘材料，并进行热退火工艺以将部分的至少一部分 与第二绝缘材料层接触的鳍片形成氧化物鳍片隔离区域。

公开(公告)号：US20160247877A1

公开(公告)日：2016-08-25

申请号：US15142145

申请日：2016-04-29

Applicant: International Business Machines Corporation

Inventor： Kern Rim ,  Junli Wang

IPC: H01L29/06 ,  H01L29/66

CPC classification number: H01L29/0649 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/845 ,  H01L23/291 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for preventing damage to the insulator layer of a semiconductor device during creation of fin field effect transistor (FinFET) includes obtaining a material stack having an active semiconductor layer, an insulator layer, and an etch stop layer between the active semiconductor layer and the insulator layer; forming a fin-array from the active semiconductor layer; patterning the fin-array; and fabricating a FinFET device from the patterned fin-array; where the etch stop layer is resistant to processes the etch stop layer is exposed to during the forming, patterning, and fabricating operations, such that the etch stop layer and the insulator layer are not damaged during the forming, patterning, and fabricating operations.

公开(公告)号：US20160233315A1

公开(公告)日：2016-08-11

申请号：US15134960

申请日：2016-04-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Darsen D. Lu ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L29/66 ,  H01L21/324 ,  H01L29/10 ,  H01L29/78 ,  H01L21/306

CPC classification number: H01L29/7846 ,  H01L21/02236 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/31051 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a fin structure that includes forming a plurality of fin structures from a bulk semiconductor substrate and forming a dielectric spacer on a sidewall of each fin structure in the plurality of fin structure. A semiconductor spacer is formed on a sidewall of the dielectric spacer. A dielectric fill is formed in the space between the adjacent fin structures. The semiconductor spacer and a portion of the fin structures that is present below a lower surface of the dielectric spacer are oxidized. Oxidizing a base portion of the fin structures produces a first strain and oxidizing the semiconductor spacer produces a second strain that is opposite the first strain.

公开(公告)号：US20160225659A1

公开(公告)日：2016-08-04

申请号：US14608729

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Bruce Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/308 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L21/76213 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/26506 ,  H01L21/3083 ,  H01L21/31155 ,  H01L21/76224 ,  H01L29/66795

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate, the fin having a lower first section that contains an oxidation-retarding implant region and an upper second section that is substantially free of the oxidation-retarding implant region, forming a sidewall spacer on opposite sides of the upper portion of the fin, forming a first layer of insulating material adjacent the sidewall spacers and the upper second section of the lower portion of the fin, and, with the first layer of insulating material in position, performing a thermal anneal process to convert the portion of the upper second section of the fin that is in contact with the first layer of insulating material into an oxide fin isolation region positioned under the fin above the lower first section of the fin.

Abstract translation: 本文公开的一种说明性方法包括在半导体衬底中形成翅片，所述翅片具有包含氧化阻滞注入区域的下部第一部分和基本上不含氧化延迟注入区域的上部第二部分 在翅片的上部的相对侧上形成侧壁间隔物，形成邻近侧壁间隔物和鳍片下部的上部第二部分的第一绝缘材料层，并且第一绝缘材料层 位置，进行热退火处理以将与第一绝缘材料层接触的翅片的上部第二部分的部分转换成位于翅片的下部第一部分下方的翅片下方的氧化物翅片隔离区域。

公开(公告)号：US20160133697A1

公开(公告)日：2016-05-12

申请号：US14980210

申请日：2015-12-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L29/08 ,  H01L29/161

CPC classification number: H01L29/0638 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of forming a semiconductor device that includes forming a gate structure on a fin structure and etching the source and drain region portions of the fin structure to provide a recessed surface. A first semiconductor layer is formed on the recessed surface of the fin structure that is doped to a first conductivity type. A leakage barrier layer is formed on the first semiconductor layer. A second semiconductor layer is formed on the leakage barrier layer. The second semiconductor layer is doped to a second conductivity type.

公开(公告)号：US09299618B1

公开(公告)日：2016-03-29

申请号：US14495342

申请日：2014-09-24

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/0924 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165

Abstract: A non-planar semiconductor structure containing semiconductor fins that are isolated from an underlying bulk silicon substrate by an epitaxial semiconductor stack is provided. The epitaxial semiconductor material stack that provides the isolation includes, from bottom to top, a semiconductor punch through stop containing at least one dopant of a conductivity type which differs from the conductivity type of the particular device region that the semiconductor fin is formed in, and a semiconductor diffusion barrier layer containing no n- or p-type dopant.

Abstract translation: 提供了包含通过外延半导体堆叠与下层体硅衬底隔离的半导体鳍片的非平面半导体结构。 提供隔离的外延半导体材料堆叠包括从底部到顶部的包含至少一种导电类型的不同于形成半导体鳍片的特定器件区域的导电类型的掺杂剂的半导体冲击穿通停止器，以及 不含n型或p型掺杂剂的半导体扩散阻挡层。

公开(公告)号：US09276113B2

公开(公告)日：2016-03-01

申请号：US14202525

申请日：2014-03-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L29/165

CPC classification number: H01L29/0638 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of forming a semiconductor device that includes forming a gate structure on a fin structure and etching the source and drain region portions of the fin structure to provide a recessed surface. A first semiconductor layer is formed on the recessed surface of the fin structure that is doped to a first conductivity type. A leakage barrier layer is formed on the first semiconductor layer. A second semiconductor layer is formed on the leakage barrier layer. The second semiconductor layer is doped to a second conductivity type.

Abstract translation: 一种形成半导体器件的方法，包括在鳍结构上形成栅极结构并蚀刻鳍结构的源极和漏极区域以提供凹陷表面。 第一半导体层形成在鳍状结构的凹入表面上，该第一半导体层被掺杂到第一导电类型。 在第一半导体层上形成漏电阻层。 在漏电阻层上形成第二半导体层。 第二半导体层被掺杂到第二导电类型。

公开(公告)号：US20150340364A1

公开(公告)日：2015-11-26

申请号：US14805529

申请日：2015-07-22

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a multilayer lattice matched structure having an unstrained layer, a first strained layer, and a second strained layer formed between the unstrained and the first strained layer. A first opening in the multilayer structure is etched and a second strained fill material having a same material as the second strained layer is deposited. A second opening in the multilayer structure is etched and an unstrained fill material having a same material as the unstrained layer is deposited. A first strained fill material having a same material as the first strained layer is then deposited between the unstrained fill and the second strained fill. A second strained fin is formed from the deposited second strained fill material, a first strained fin is formed from the deposited first strained fill material, and an unstrained fin is formed from the deposited unstrained fill material.